VLSI-SoC: From Algorithms to Circuits and System-on-Chip Design 20th IFIP WG 10.5/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2012, Santa Cruz, CA, USA, October 7-10, 2012, Revised Selected Papers /
This book contains extended and revised versions of the best papers presented at the 20th IFIP WG 10.5/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2012, held in Santa Cruz, CA, USA, in October 2012. The 12 papers included in the book were carefully reviewed and selected f...
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| Tác giả của công ty: | |
|---|---|
| Tác giả khác: | , , , , |
| Định dạng: | Điện tử eBook |
| Ngôn ngữ: | English |
| Được phát hành: |
Berlin, Heidelberg :
Springer Berlin Heidelberg : Imprint: Springer,
2013.
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| Phiên bản: | 1st ed. 2013. |
| Loạt: | IFIP Advances in Information and Communication Technology,
418 |
| Những chủ đề: | |
| Truy cập trực tuyến: | https://doi.org/10.1007/978-3-642-45073-0 |
| Các nhãn: |
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Mục lục:
- FPGA-Based High-Speed Authenticated Encryption System
- A Smart Memory Accelerated Computed Tomography Parallel Backprojection
- Trinocular Stereo Vision Using a Multi Level Hierarchical Classification Structure
- Spatially-Varying Image Warping: Evaluations and VLSI Implementations
- An Ultra-Low-Power Application-Specific Processor with Sub-VT Memories for Compressed Sensing
- Configurable Low-Latency Interconnect for Multi-core Clusters
- A Hexagonal Processor and Interconnect Topology for Many-Core Architecture with Dense On-Chip Networks
- Fault-Tolerant Techniques to Manage Yield and Power Constraints in Network-on-Chip Interconnections
- On the Automatic Generation of Software-Based Self-Test Programs for Functional Test and Diagnosis of VLIW Processors
- SEU-Aware Low-Power Memories Using a Multiple Supply Voltage Array Architecture
- CMOS Implementation of Threshold Gates with Hysteresis
- Simulation and Experimental Characterization of a Unified Memory Device with Two Floating-Gates.