Real time plate recognition for motorcycle using field programmable gate array
The aim of this project is to develop motorcycle plate image detection and recognition framework for traffic offender using Field Programmable Gate Array (FPGA). The proposed system has processing time of 33.3 milliseconds in various critical conditions, such as daylight, rainy daylight and night...
Wedi'i Gadw mewn:
| Prif Awdur: | |
|---|---|
| Fformat: | Thesis |
| Iaith: | English |
| Cyhoeddwyd: |
2019
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| Pynciau: | |
| Mynediad Ar-lein: | http://psasir.upm.edu.my/id/eprint/99237/1/ITMA%202020%2013%20IR.pdf |
| Tagiau: |
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