Search Results - parallel instruction processor functionality function https

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processor functionality » processing functionality , receptor functionality , processes functionalities
functionality function » functionals function , functionaries function , functional functions
instruction processor » instruction processing , construction processes , construction process
parallel instruction » parallel construction , parallel intrusion , parallel insertion
function https » functions https , fiction https

Network and Parallel Computing IFIP International Conference, NPC 2005, Beijing, China, November 30 - December 3, 2005, Proceedings /

Published 2005

Table of Contents: “... Optical Networks -- A Parallel O(n27n/8) Time-Memory-Processor Tradeoff for Knapsack-Like Problems...”
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Languages and Compilers for Parallel Computing 18th International Workshop, LCPC 2005, Hawthorne, NY, USA, October 20-22, 2005, Revised Selected Papers /

Published 2006

Table of Contents: “... Domain Specific Language on Network Processors -- Array Replication to Increase Parallelism...”
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Embedded Computer Systems: Architectures, Modeling, and Simulation 6th International Workshop, SAMOS 2006, Samos, Greece, July 17-20, 2006, Proceedings /

Published 2006

Table of Contents: “... Spaces with Massively Parallel Embedded Processors -- Efficient Automated Clock Gating Using CoDeL...”
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High-Performance Computing 6th International Symposium, ISHPC 2005, Nara, Japan, September 7-9, 2005, First International Workshop on Advance Low Power Systems, ALPS 2006, Revised...

Published 2008

Table of Contents: “... -- Exploiting Execution Locality with a Decoupled Kilo-Instruction Processor -- Decoupled State-Execute...”
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Reconfigurable Computing: Architectures, Tools, and Applications 4th International Workshop, ARC 2008, London, UK, March 26-28, 2008, Proceedings /

Published 2008

Table of Contents: “... Synthesis with Cancel Tokens -- Instruction Set Extension -- ARISE Machines: Extending Processors...”
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High Performance Embedded Architectures and Compilers Third International Conference, HiPEAC 2008, Göteborg, Sweden, January 27-29, 2008, Proceedings /

Published 2008

Table of Contents: “... Processor with Variable Length Instructions -- Experiences with Parallelizing a Bio-informatics Program...”
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Advances in Computer Systems Architecture 11th Asia-Pacific Conference, ACSAC 2006, Shanghai, China, September 6-8, 2006, Proceedings /

Published 2006

Table of Contents: “... for Coordinating Data-Parallel Programs (Position Statement) -- Implementations of Square-Root and Exponential...”
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Embedded Computer Systems: Architectures, Modeling, and Simulation 8th International Workshop, SAMOS 2008, Samos, Greece, July 21-24, 2008, Proceedings /

Published 2008

Table of Contents: “... Different Cache Levels in a Soft Real-Time SMT Processor -- Impact of Software Bypassing on Instruction...”
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Embedded Computer Systems: Architectures, Modeling, and Simulation 7th International Workshop, SAMOS 2007, Samos, Greece, July 16-19, 2007, Proceedings /

Published 2007

Table of Contents: “... on a Massively Parallel Embedded Processor -- Stream Image Processing on a Dual-Core Embedded System...”
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Advances in Computer Systems Architecture 12th Asia-Pacific Conference, ACSAC 2007, Seoul, Korea, August 23-25, 2007, Proceedings /

Published 2007

Table of Contents: “... Processor Architecture Using Asynchronous Function Units -- A Bypass Mechanism to Enhance Branch Predictor...”
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Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation 17th International Workshop, PATMOS 2007, Gothenburg, Sweden, September 3-5, 2007, Proc...

Published 2007

Table of Contents: “... on the TTA -- Asynchronous Functional Coupling for Low Power Sensor Network Processors -- A Heuristic...”
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Computer Science -- Theory and Applications First International Symposium on Computer Science in Russia, CSR 2006, St. Petersburg, Russia, June 8-12, 2006, Proceedings /

Published 2006

Table of Contents: “... -- Instruction Selection for ARM/Thumb Processors Based on a Multi-objective Ant Algorithm -- A New Flow Control...”
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Architecture of Computing Systems -- ARCS 2013 26th International Conference, Prague, Czech Republic, February 19-22, 2013 Proceedings /

Published 2013

Table of Contents: “...-virtualized CAN Controller for Multi-core Processors in Real-Time Applications -- Shrinking L1 Instruction...”
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Reconfigurable Computing: Architectures, Tools and Applications 6th International Symposium, ARC 2010, Bangkok, Thailand, March 17-19, 2010, Proceedings /

Published 2010

Table of Contents: “... -- Architecture-Aware Custom Instruction Generation for Reconfigurable Processors -- Cost and Performance...”
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Applied Reconfigurable Computing 11th International Symposium, ARC 2015, Bochum, Germany, April 13-17, 2015, Proceedings /

Published 2015

Table of Contents: “... Instruction Memory Cache Blocks -- A Vector Caching Scheme for Streaming FPGA SpMV Accelerators...”
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Automatic SIMD Vectorization of SSA-based Control Flow Graphs

by Karrenberg, Ralf., Karrenberg, Ralf.
Published 2015

Subjects: “...Programming Languages, Compilers, Interpreters. https://scigraph.springernature.com/ontologies...”
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Emerging Trends in Computing, Informatics, Systems Sciences, and Engineering

Published 2013

Table of Contents: “... Environment -- The Analysis of the Efficiency of Parallelization of Existing Serial Code on the Basis...”
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