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Intelligent Information Processing and Web Mining Proceedings of the International IIS: IIPWM´06 Conference held in Ustron, Poland, June 19-22, 2006 /

Published 2006

Table of Contents: “... of a Simple Genetic xsAlgorithm -- Evolutionary Algorithm of Radial Basis Function Neural Networks...”
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Intelligent Computing, Networking, and Informatics Proceedings of the International Conference on Advanced Computing, Networking, and Informatics, India, June 2013 /

Published 2014

Table of Contents: “... by Phase Tracking using Bilateral Probability Function -- Electrical Network Modeling of Amino Acid String...”
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High Performance Embedded Architectures and Compilers Third International Conference, HiPEAC 2008, Göteborg, Sweden, January 27-29, 2008, Proceedings /

Published 2008

Table of Contents: “... Processor with Variable Length Instructions -- Experiences with Parallelizing a Bio-informatics Program...”
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Discovery Science 9th International Conference, DS 2006, Barcelona, Spain, October 7-10, 2006, Proceedings /

Published 2006

Table of Contents: “... Inductive Logic Programming from Multiple Genome Databases -- Clustering Pairwise Distances with Missing...”
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Advances in Computer Systems Architecture 11th Asia-Pacific Conference, ACSAC 2006, Shanghai, China, September 6-8, 2006, Proceedings /

Published 2006

Table of Contents: “... for Coordinating Data-Parallel Programs (Position Statement) -- Implementations of Square-Root and Exponential...”
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The Semantic Web: Research and Applications 7th European Semantic Web Conference, ESWC 2010, Heraklion, Crete, Greece, May 30 - June 3, 2010, Proceedings, Part II /

Published 2010

Table of Contents: “... Correctness -- Efficient Semantic Event Processing: Lessons Learned in User Interface Integration -- Usage...”
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Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation 17th International Workshop, PATMOS 2007, Gothenburg, Sweden, September 3-5, 2007, Proc...

Published 2007

Table of Contents: “... Measurements -- A Flexible General-Purpose Parallelizing Architecture for Nested Loops in Reconfigurable...”
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