Search Results - parallel processor accelerating function function https

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processor accelerating » processors accelerating , process accelerating , coprocessors accelerating
accelerating function » acceleration function , accelerated function , accelerating action
parallel processor » parallel processors , parallel processes , parallel process
function function » function functional , functions functional , function dysfunction
function https » functions https , fiction https

Network and Parallel Computing IFIP International Conference, NPC 2005, Beijing, China, November 30 - December 3, 2005, Proceedings /

Published 2005

Table of Contents: “... Optical Networks -- A Parallel O(n27n/8) Time-Memory-Processor Tradeoff for Knapsack-Like Problems...”
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Parallel Computing Technologies 9th International Conference, PaCT 2007, Pereslavl-Zalessky, Russia, September 3-7, 2007, Proceedings /

Published 2007

Table of Contents: “... of Optimal Matrix Partitioning for Parallel Dense Factorization on Heterogeneous Processors -- Parallel...”
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Algorithms and Architectures for Parallel Processing 10th International Conference, ICA3PP 2010, Busan, Korea, May 21-23, 2010. Proceedings, Part I /

Published 2010

Table of Contents: “... in Distributed Environments by Simultaneous Fragmentation and Allocation -- Parallel Architectures -- Function...”
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Languages and Compilers for Parallel Computing 22nd International Workshop, LCPC 2009, Newark, DE, USA, October 8-10, 2009, Revised Selected Papers /

Published 2010

Table of Contents: “...A Communication Framework for Fault-Tolerant Parallel Execution -- The STAPL pList -- Hardware...”
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Algorithms and Architectures for Parallel Processing 10th International Conference, ICA3PP 2010, Busan, Korea, May 21-23, 2010. Workshops, Part II /

Published 2010

Table of Contents: “...) -- Accelerating Euler Equations Numerical Solver on Graphics Processing Units -- An Improved Parallel MEMS...”
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Euro-Par 2009, Parallel Processing - Workshops HPPC, HeteroPar, PROPER, ROIA, UNICORE, VHPC, Delft, The Netherlands, August 25-28, 2009, Workshops /

Published 2010

Table of Contents: “... on Heterogeneous Processors Based on Their Functional Performance Models -- Accelerating S3D: A GPGPU Case Study...”
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Reconfigurable Computing: Architectures, Tools, and Applications 4th International Workshop, ARC 2008, London, UK, March 26-28, 2008, Proceedings /

Published 2008

Table of Contents: “... Environment on Dynamically Reconfigurable Processor -- Accelerating Speculative Execution in High-Level...”
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High Performance Embedded Architectures and Compilers Third International Conference, HiPEAC 2008, Göteborg, Sweden, January 27-29, 2008, Proceedings /

Published 2008

Table of Contents: “... Parallelism on Heterogeneous Multi-core Processors: A Case Study of the Cell BE -- IIa Reconfigurable - ASIP...”
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Advances in Computer Systems Architecture 11th Asia-Pacific Conference, ACSAC 2006, Shanghai, China, September 6-8, 2006, Proceedings /

Published 2006

Table of Contents: “... for Coordinating Data-Parallel Programs (Position Statement) -- Implementations of Square-Root and Exponential...”
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Advances in Computer Systems Architecture 12th Asia-Pacific Conference, ACSAC 2007, Seoul, Korea, August 23-25, 2007, Proceedings /

Published 2007

Table of Contents: “... Processor Architecture Using Asynchronous Function Units -- A Bypass Mechanism to Enhance Branch Predictor...”
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Architecture of Computing Systems - ARCS 2007 20th International Conference, Zurich, Switzerland, March 12-15, 2007, Proceedings /

Published 2007

Table of Contents: “...A Reconfigurable Processor for Forward Error Correction -- FPGA-Accelerated Deletion-Tolerant...”
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Reconfigurable Computing: Architectures, Tools and Applications 6th International Symposium, ARC 2010, Bangkok, Thailand, March 17-19, 2010, Proceedings /

Published 2010

Table of Contents: “...Keynotes (Abstracts) -- High-Performance Energy-Efficient Reconfigurable Accelerators/Co-processors...”
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Correct Hardware Design and Verification Methods 13th IFIP WG 10.5Advanced Research, Working Conference, CHARME 2005, Saarbrücken, Germany, October 3-6, 2005, Proceedings /

Published 2005

Table of Contents: “... for Pipelined Processors with Multicycle Functional Units -- Algorithms and Techniques for Speeding (DD-Based...”
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Evolvable Systems: From Biology to Hardware 7th International Conference, ICES 2007, Wuhan, China, September 21-23, 2007, Proceedings /

Published 2007

Table of Contents: “... Cores to Evolve Combinational Logic Circuits in Parallel -- An Intrinsic Evolvable Hardware Based...”
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High Performance Computing - HiPC 2008 15th International Conference, Bangalore, India, December 17-20, 2008, Proceedings /

Published 2008

Table of Contents: “... of Emerging Parallel Media Mining Workloads -- Efficient PDM Sorting Algorithms -- Accelerating Cone Beam...”
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VLSI-SoC: From Algorithms to Circuits and System-on-Chip Design 20th IFIP WG 10.5/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2012, Santa Cruz, CA, USA,...

Published 2013

Table of Contents: “... Programs for Functional Test and Diagnosis of VLIW Processors -- SEU-Aware Low-Power Memories Using a...”
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Architecture of Computing Systems -- ARCS 2013 26th International Conference, Prague, Czech Republic, February 19-22, 2013 Proceedings /

Published 2013

Table of Contents: “...: The Programming Model for Future Many-Core Processors -- A Highly Dependable Self-adaptive Mixed-Signal Multi-core...”
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Computational Science - ICCS 2007 7th International Conference, Beijing China, May 27-30, 2007, Proceedings, Part I /

Published 2007

Table of Contents: “... Applications on the Stream Processor -- A Scalable Parallel Software Volume Rendering Algorithm for Large-Scale...”
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High Performance Computing Systems and Applications 23rd International Symposium, HPCS 2009, Kingston, Ontario, Canada, June 14-17, 2009, Revised Selected Papers /

Published 2010

Table of Contents: “... Mechanics -- A Hybrid Parallel Algorithm for Transforming Finite Element Functions from Adaptive...”
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Applied Reconfigurable Computing 11th International Symposium, ARC 2015, Bochum, Germany, April 13-17, 2015, Proceedings /

Published 2015

Table of Contents: “... Instruction Memory Cache Blocks -- A Vector Caching Scheme for Streaming FPGA SpMV Accelerators...”
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