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Network and Parallel Computing IFIP International Conference, NPC 2005, Beijing, China, November 30 - December 3, 2005, Proceedings /

Published 2005

Table of Contents: “... Optical Networks -- A Parallel O(n27n/8) Time-Memory-Processor Tradeoff for Knapsack-Like Problems...”
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Parallel Computing Technologies 9th International Conference, PaCT 2007, Pereslavl-Zalessky, Russia, September 3-7, 2007, Proceedings /

Published 2007

Table of Contents: “... of Optimal Matrix Partitioning for Parallel Dense Factorization on Heterogeneous Processors -- Parallel...”
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Languages and Compilers for Parallel Computing 18th International Workshop, LCPC 2005, Hawthorne, NY, USA, October 20-22, 2005, Revised Selected Papers /

Published 2006

Table of Contents: “... Domain Specific Language on Network Processors -- Array Replication to Increase Parallelism...”
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Parallel Processing and Applied Mathematics, Part II 8th International Conference, PPAM 2009, Wroclaw, Poland, September 13-16, 2009, Proceedings /

Published 2010

Table of Contents: “...Workshop on Scheduling for Parallel Computing (SPC 2009) -- Fully Polynomial Time Approximation...”
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VLSI-SoC: From Algorithms to Circuits and System-on-Chip Design 20th IFIP WG 10.5/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2012, Santa Cruz, CA, USA, October 7-10, 2012...

Published 2013

Table of Contents: “... Programs for Functional Test and Diagnosis of VLIW Processors -- SEU-Aware Low-Power Memories Using a...”
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Embedded Computer Systems: Architectures, Modeling, and Simulation 6th International Workshop, SAMOS 2006, Samos, Greece, July 17-20, 2006, Proceedings /

Published 2006

Table of Contents: “... Spaces with Massively Parallel Embedded Processors -- Efficient Automated Clock Gating Using CoDeL...”
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High Performance Embedded Architectures and Compilers Third International Conference, HiPEAC 2008, Göteborg, Sweden, January 27-29, 2008, Proceedings /

Published 2008

Table of Contents: “... Parallelism on Heterogeneous Multi-core Processors: A Case Study of the Cell BE -- IIa Reconfigurable - ASIP...”
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Embedded Computer Systems: Architectures, Modeling, and Simulation 8th International Workshop, SAMOS 2008, Samos, Greece, July 21-24, 2008, Proceedings /

Published 2008

Table of Contents: “... Systems -- Streaming Systems in FPGAs -- Heterogeneous Design in Functional DIF -- Tool Integration...”
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Computer Aided Systems Theory – EUROCAST 2005 10th International Conference on Computer Aided Systems Theory, Las Palmas de Gran Canaria, Spain, February 7-11, 2005, Revised Select...

Published 2005

Table of Contents: “... Through Span Composition -- Degenerate Arrays: A Framework for Uncertain Data Tables -- Neural Network...”
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Embedded Computer Systems: Architectures, Modeling, and Simulation 7th International Workshop, SAMOS 2007, Samos, Greece, July 16-19, 2007, Proceedings /

Published 2007

Table of Contents: “...Keynotes -- Software Is the Answer But What Is the Question? -- Integrating VLIW Processors with a...”
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Reconfigurable Computing: Architectures, Tools and Applications 6th International Symposium, ARC 2010, Bangkok, Thailand, March 17-19, 2010, Proceedings /

Published 2010

Table of Contents: “... -- Generic Systolic Array for Run-Time Scalable Cores -- Virtualization within a Parallel Array...”
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Artificial Evolution 9th International Conference, Evolution Artificielle, EA 2009, Strasbourg, France, October 26-28, 2009. Revised Selected Papers /

Published 2010

Table of Contents: “... -- Parallelization of an Evolutionary Algorithm on a Platform with Multi-core Processors -- On the Difficulty...”
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Large-Scale Scientific Computing 8th International Conference, LSSC 2011, Sozopol, Bulgaria, June 6-10th, 2011. Revised Selected Papers /

Published 2012

Table of Contents: “... and Applications to Aerodynamics .-Processor Array Design with the Use of Genetic Algorithm.-A Hybrid Genetic...”
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Applied Reconfigurable Computing 11th International Symposium, ARC 2015, Bochum, Germany, April 13-17, 2015, Proceedings /

Published 2015

Table of Contents: “... on an Optically Reconfigurable Gate Array -- Exploring Dynamic Reconfigurable CORDIC Co-Processors Tightly Coupled...”
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Emerging Trends in Computing and Communication ETCC 2014, March 22-23, 2014 /

Published 2014

Table of Contents: “... -- Exploring Chaotic Neural Network for Cryptographic Hash Function -- Protocol to Authenticate the Objects...”
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Embedded System Design: Topics, Techniques and Trends IFIP TC10 Working Conference: International Embedded Systems Symposium (IESS), May 30 - June 1, 2007, Irvine (CA), USA /

Published 2007

Table of Contents: “...-Processor Systems with Static Priorities -- Approach for a Formal Verification of a Bit-serial Pipelined...”
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