Search Results - parallel processor chips functionality function https

1

Multicore Systems On-Chip: Practical Software/Hardware Design

by Ben Abdallah, Abderazek., Ben Abdallah, Abderazek.
Published 2013

Table of Contents: “...Introduction to Multicore Systems On-Chip -- Multicore SoCs Design Methods -- Multicore SoC...”
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2

MULTICORE SYSTEMS ON-CHIP

by Abderazek, Ben Abadallah., Abderazek, Ben Abadallah.
Published 2010

Table of Contents: “...- and Many-Core Systems -- Parallelizing Compiler for High Performance Computing -- Dual-Execution Processor...”
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3

Network and Parallel Computing IFIP International Conference, NPC 2010, Zhengzhou, China, September 13-15, 2010, Proceedings /

Published 2010

Table of Contents: “... References on Cell Multicore Processor -- Software-Hardware Cooperative DRAM Bank Partitioning for Chip...”
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4

Languages and Compilers for Parallel Computing 22nd International Workshop, LCPC 2009, Newark, DE, USA, October 8-10, 2009, Revised Selected Papers /

Published 2010

Table of Contents: “...A Communication Framework for Fault-Tolerant Parallel Execution -- The STAPL pList -- Hardware...”
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5

Algorithms and Architectures for Parallel Processing 10th International Conference, ICA3PP 2010, Busan, Korea, May 21-23, 2010. Proceedings, Part I /

Published 2010

Table of Contents: “... in Distributed Environments by Simultaneous Fragmentation and Allocation -- Parallel Architectures -- Function...”
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6

Algorithms and Architectures for Parallel Processing 10th International Conference, ICA3PP 2010, Busan, Korea, May 21-23, 2010. Workshops, Part II /

Published 2010

Table of Contents: “...The 2010 International Symposium on Frontiers of Parallel and Distributed Computing (FPDC 2010...”
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7

Euro-Par 2009, Parallel Processing - Workshops HPPC, HeteroPar, PROPER, ROIA, UNICORE, VHPC, Delft, The Netherlands, August 25-28, 2009, Workshops /

Published 2010

Table of Contents: “...Third Workshop on Highly Parallel Processing on a Chip (HPPC 2009) -- HPPC 2009: 3rd Workshop...”
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8

VLSI-SoC: From Algorithms to Circuits and System-on-Chip Design 20th IFIP WG 10.5/IEEE...

Published 2013

Table of Contents: “... Programs for Functional Test and Diagnosis of VLIW Processors -- SEU-Aware Low-Power Memories Using a...”
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9

From Model-Driven Design to Resource Management for Distributed Embedded Systems IFIP TC 10 Working Conference on Distributed and Parallel Embedded Systems (DIPES 2006) October 11-13, 2006, Braga, Portugal /

Published 2006

Table of Contents: “...Design Challenges in Multiprocessor Systems-on-Chip -- Some Issues in Model-Based Development...”
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10

High-Performance Computing 6th International Symposium, ISHPC 2005, Nara, Japan, September 7-9, 2005, First International Workshop on Advance Low Power Systems, ALPS 2006, Revised...

Published 2008

Table of Contents: “... -- Exploiting Execution Locality with a Decoupled Kilo-Instruction Processor -- Decoupled State-Execute...”
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11

Advances in Computer Systems Architecture 11th Asia-Pacific Conference, ACSAC 2006, Shanghai, China, September 6-8, 2006, Proceedings /

Published 2006

Table of Contents: “... for Programming Chip Multiprocessors -- Functional Unit Chaining: A Runtime Adaptive Architecture for Reducing...”
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12

Advances in Computer Systems Architecture 12th Asia-Pacific Conference, ACSAC 2007, Seoul, Korea, August 23-25, 2007, Proceedings /

Published 2007

Table of Contents: “... Processor Architecture Using Asynchronous Function Units -- A Bypass Mechanism to Enhance Branch Predictor...”
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Embedded Computer Systems: Architectures, Modeling, and Simulation 7th International Workshop, SAMOS 2007, Samos, Greece, July 16-19, 2007, Proceedings /

Published 2007

Table of Contents: “... on a Massively Parallel Embedded Processor -- Stream Image Processing on a Dual-Core Embedded System...”
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High Performance Embedded Architectures and Compilers Third International Conference, HiPEAC 2008, Göteborg, Sweden, January 27-29, 2008, Proceedings /

Published 2008

Table of Contents: “... Processing -- rMPI: Message Passing on Multicore Processors with On-Chip Interconnect -- Modeling Multigrain...”
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15

Reconfigurable Computing: Architectures, Tools, and Applications 4th International Workshop, ARC 2008, London, UK, March 26-28, 2008, Proceedings /

Published 2008

Table of Contents: “...Keynotes -- Synthesizing FPGA Circuits from Parallel Programs -- From Silicon to Science: The Long...”
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Embedded Computer Systems: Architectures, Modeling, and Simulation 8th International Workshop, SAMOS 2008, Samos, Greece, July 21-24, 2008, Proceedings /

Published 2008

Table of Contents: “... Different Cache Levels in a Soft Real-Time SMT Processor -- Impact of Software Bypassing on Instruction...”
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Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation 17th International Workshop, PATMOS 2007, Gothenburg, Sweden, September 3-5, 2007, Proc...

Published 2007

Table of Contents: “... on the TTA -- Asynchronous Functional Coupling for Low Power Sensor Network Processors -- A Heuristic...”
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18

Transactions on High-Performance Embedded Architectures and Compilers IV

Published 2011

Table of Contents: “...: Exemplified Using Graphics Processors -- Microvisor: A Runtime Architecture for Thermal Management in Chip...”
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Architecture of Computing Systems -- ARCS 2013 26th International Conference, Prague, Czech Republic, February 19-22, 2013 Proceedings /

Published 2013

Table of Contents: “...: The Programming Model for Future Many-Core Processors -- A Highly Dependable Self-adaptive Mixed-Signal Multi-core...”
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Architecture of Computing Systems - ARCS 2006 19th International Conference, Frankfurt/Main, Germany, March 13-16, 2006, Proceedings /

Published 2006

Table of Contents: “... Destructive-Read DRAM -- A Processor Architecture with Effective Memory System for Sort-Last Parallel...”
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