Search Results - parallel processor efficient functioning function https

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efficient functioning » efficient functional , coefficient functionals , efficient partitioning
functioning function » functioning functional , function function , functionals function
processor efficient » processors efficient , processes efficient , processing efficient
parallel processor » parallel processors , parallel processes , parallel process
function https » functions https , fiction https

Network and Parallel Computing IFIP International Conference, NPC 2010, Zhengzhou, China, September 13-15, 2010, Proceedings /

Published 2010

Table of Contents: “...-Performance of Multi-core Processors -- Internet-Based Virtual Computing Environment -- Session 1...”
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Network and Parallel Computing IFIP International Conference, NPC 2005, Beijing, China, November 30 - December 3, 2005, Proceedings /

Published 2005

Table of Contents: “... on Efficient Index Techniques -- A Parallel Routing Algorithm on Circulant Networks Employing the Hamiltonian...”
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Parallel Computing Technologies 9th International Conference, PaCT 2007, Pereslavl-Zalessky, Russia, September 3-7, 2007, Proceedings /

Published 2007

Table of Contents: “... of Optimal Matrix Partitioning for Parallel Dense Factorization on Heterogeneous Processors -- Parallel...”
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Languages and Compilers for Parallel Computing 18th International Workshop, LCPC 2005, Hawthorne, NY, USA, October 20-22, 2005, Revised Selected Papers /

Published 2006

Table of Contents: “... Domain Specific Language on Network Processors -- Array Replication to Increase Parallelism...”
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Algorithms and Architectures for Parallel Processing 10th International Conference, ICA3PP 2010, Busan, Korea, May 21-23, 2010. Proceedings, Part I /

Published 2010

Table of Contents: “... in Distributed Environments by Simultaneous Fragmentation and Allocation -- Parallel Architectures -- Function...”
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Languages and Compilers for Parallel Computing 22nd International Workshop, LCPC 2009, Newark, DE, USA, October 8-10, 2009, Revised Selected Papers /

Published 2010

Table of Contents: “...A Communication Framework for Fault-Tolerant Parallel Execution -- The STAPL pList -- Hardware...”
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Algorithms and Architectures for Parallel Processing 10th International Conference, ICA3PP 2010, Busan, Korea, May 21-23, 2010. Workshops, Part II /

Published 2010

Table of Contents: “...) -- Efficient Grid on the OTIS-Arrangment Network -- Single Thread Program Parallelism with Dataflow Abstracting...”
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Euro-Par 2009, Parallel Processing - Workshops HPPC, HeteroPar, PROPER, ROIA, UNICORE, VHPC, Delft, The Netherlands, August 25-28, 2009, Workshops /

Published 2010

Table of Contents: “... on Partial Estimation of Their Functional Performance Models -- An Efficient Weighted Bi-objective Scheduling...”
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Multicore Systems On-Chip: Practical Software/Hardware Design

by Ben Abdallah, Abderazek., Ben Abdallah, Abderazek.
Published 2013

Table of Contents: “... NoCs -- Parallelizing Compiler for Single and Multicore Computing -- Power Optimization Techniques...”
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Turbo Decoder Architecture for Beyond-4G Applications

by Wong, Cheng-Chi., Wong, Cheng-Chi., Chang, Hsie-Chia.
Published 2014

Table of Contents: “... Processing -- Low-Complexity Solution for Highly Parallel Architecture -- High Efficiency Solution for Highly...”
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From Model-Driven Design to Resource Management for Distributed Embedded Systems IFIP TC 10 Working Conference on Distributed and Parallel Embedded Systems (DIPES 2006) October 11-13, 2006, Braga, Portugal /

Published 2006

Table of Contents: “... Nodes -- Transient Processor/Bus Fault Tolerance for Embedded Systems -- Distributed Timed Multitasking...”
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Embedded Computer Systems: Architectures, Modeling, and Simulation 6th International Workshop, SAMOS 2006, Samos, Greece, July 17-20, 2006, Proceedings /

Published 2006

Table of Contents: “... Spaces with Massively Parallel Embedded Processors -- Efficient Automated Clock Gating Using CoDeL...”
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High-Performance Computing 6th International Symposium, ISHPC 2005, Nara, Japan, September 7-9, 2005, First International Workshop on Advance Low Power Systems, ALPS 2006, Revised...

Published 2008

Table of Contents: “... Efficient Parallel Matrix-Matrix Multiplication on the Torus -- A New Dynamic Load Balancing Technique...”
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Advances in Computer Systems Architecture 11th Asia-Pacific Conference, ACSAC 2006, Shanghai, China, September 6-8, 2006, Proceedings /

Published 2006

Table of Contents: “... for SMT Processors -- The New BCD Subtractor and Its Reversible Logic Implementation -- Power-Efficient...”
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Reconfigurable Computing: Architectures, Tools, and Applications 4th International Workshop, ARC 2008, London, UK, March 26-28, 2008, Proceedings /

Published 2008

Table of Contents: “... with Multi-seeds Detection and Parallel Extension -- Highly Space Efficient Counters for Perl Compatible...”
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Embedded Computer Systems: Architectures, Modeling, and Simulation 8th International Workshop, SAMOS 2008, Samos, Greece, July 21-24, 2008, Proceedings /

Published 2008

Table of Contents: “... -- On the Benefit of Caching Traffic Flow Data in the Link Buffer -- Energy-Efficient Simultaneous Thread Fetch from...”
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Embedded Computer Systems: Architectures, Modeling, and Simulation 7th International Workshop, SAMOS 2007, Samos, Greece, July 16-19, 2007, Proceedings /

Published 2007

Table of Contents: “... on a Massively Parallel Embedded Processor -- Stream Image Processing on a Dual-Core Embedded System...”
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Advances in Computer Systems Architecture 12th Asia-Pacific Conference, ACSAC 2007, Seoul, Korea, August 23-25, 2007, Proceedings /

Published 2007

Table of Contents: “...A Compiler Framework for Supporting Speculative Multicore Processors -- Power-Efficient...”
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Computer Aided Systems Theory – EUROCAST 2005 10th International Conference on Computer Aided Systems Theory, Las Palmas de Gran Canaria, Spain, February 7-11, 2005, Revised Select...

Published 2005

Table of Contents: “... Information -- Intelligent Information Systems -- On Recursive Functions and Well–Founded Relations...”
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Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation 17th International Workshop, PATMOS 2007, Gothenburg, Sweden, September 3-5, 2007, Proc...

Published 2007

Table of Contents: “... on the TTA -- Asynchronous Functional Coupling for Low Power Sensor Network Processors -- A Heuristic...”
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