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parallel processor » parallel processors , parallel processes , parallel process
processor platform » processor platforms , process platform , processing platform
function https » functions https , fiction https

Network and Parallel Computing IFIP International Conference, NPC 2010, Zhengzhou, China, September 13-15, 2010, Proceedings /

Published 2010

Table of Contents: “...-Performance of Multi-core Processors -- Internet-Based Virtual Computing Environment -- Session 1...”
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Languages and Compilers for Parallel Computing 18th International Workshop, LCPC 2005, Hawthorne, NY, USA, October 20-22, 2005, Revised Selected Papers /

Published 2006

Table of Contents: “... Domain Specific Language on Network Processors -- Array Replication to Increase Parallelism...”
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Algorithms and Architectures for Parallel Processing 10th International Conference, ICA3PP 2010, Busan, Korea, May 21-23, 2010. Proceedings, Part I /

Published 2010

Table of Contents: “... in Distributed Environments by Simultaneous Fragmentation and Allocation -- Parallel Architectures -- Function...”
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Algorithms and Architectures for Parallel Processing 10th International Conference, ICA3PP 2010, Busan, Korea, May 21-23, 2010. Workshops, Part II /

Published 2010

Table of Contents: “...-core Platforms -- A Paradigm for Processing Network Protocols in Parallel -- Real-Time Task Scheduling...”
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Platform Based Design at the Electronic System Level Industry Perspectives and Experiences /

Published 2006

Table of Contents: “... -- The Configurable Processor View of Platform Provision -- Peripheral Modeling for Platform Driven ESL Design...”
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Euro-Par 2009, Parallel Processing - Workshops HPPC, HeteroPar, PROPER, ROIA, UNICORE, VHPC, Delft, The Netherlands, August 25-28, 2009, Workshops /

Published 2010

Table of Contents: “...? -- Distance Constrained Mapping to Support NoC Platforms Based on Source Routing -- Parallel Variable-Length...”
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From Model-Driven Design to Resource Management for Distributed Embedded Systems IFIP TC 10 Working Conference on Distributed and Parallel Embedded Systems (DIPES 2006) October 11-13, 2006, Braga, Portugal /

Published 2006

Table of Contents: “... Nodes -- Transient Processor/Bus Fault Tolerance for Embedded Systems -- Distributed Timed Multitasking...”
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Embedded Computer Systems: Architectures, Modeling, and Simulation 6th International Workshop, SAMOS 2006, Samos, Greece, July 17-20, 2006, Proceedings /

Published 2006

Table of Contents: “... Spaces with Massively Parallel Embedded Processors -- Efficient Automated Clock Gating Using CoDeL...”
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High-Performance Computing 6th International Symposium, ISHPC 2005, Nara, Japan, September 7-9, 2005, First International Workshop on Advance Low Power Systems, ALPS 2006, Revised...

Published 2008

Table of Contents: “... -- Exploiting Execution Locality with a Decoupled Kilo-Instruction Processor -- Decoupled State-Execute...”
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Reconfigurable Computing: Architectures, Tools, and Applications 4th International Workshop, ARC 2008, London, UK, March 26-28, 2008, Proceedings /

Published 2008

Table of Contents: “...Keynotes -- Synthesizing FPGA Circuits from Parallel Programs -- From Silicon to Science: The Long...”
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High Performance Embedded Architectures and Compilers Third International Conference, HiPEAC 2008, Göteborg, Sweden, January 27-29, 2008, Proceedings /

Published 2008

Table of Contents: “... Parallelism on Heterogeneous Multi-core Processors: A Case Study of the Cell BE -- IIa Reconfigurable - ASIP...”
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Embedded Computer Systems: Architectures, Modeling, and Simulation 7th International Workshop, SAMOS 2007, Samos, Greece, July 16-19, 2007, Proceedings /

Published 2007

Table of Contents: “... on a Massively Parallel Embedded Processor -- Stream Image Processing on a Dual-Core Embedded System...”
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Embedded Computer Systems: Architectures, Modeling, and Simulation 8th International Workshop, SAMOS 2008, Samos, Greece, July 21-24, 2008, Proceedings /

Published 2008

Table of Contents: “... Different Cache Levels in a Soft Real-Time SMT Processor -- Impact of Software Bypassing on Instruction...”
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Advances in Computer Systems Architecture 12th Asia-Pacific Conference, ACSAC 2007, Seoul, Korea, August 23-25, 2007, Proceedings /

Published 2007

Table of Contents: “... Processor Architecture Using Asynchronous Function Units -- A Bypass Mechanism to Enhance Branch Predictor...”
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Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation 17th International Workshop, PATMOS 2007, Gothenburg, Sweden, September 3-5, 2007, Proc...

Published 2007

Table of Contents: “... on the TTA -- Asynchronous Functional Coupling for Low Power Sensor Network Processors -- A Heuristic...”
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Transactions on High-Performance Embedded Architectures and Compilers IV

Published 2011

Table of Contents: “... Transactional Memory -- A Parallelizing Compiler Cooperative Heterogeneous Multicore Processor Architecture -- A...”
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Artificial Evolution 9th International Conference, Evolution Artificielle, EA 2009, Strasbourg, France, October 26-28, 2009. Revised Selected Papers /

Published 2010

Table of Contents: “... -- Parallelization of an Evolutionary Algorithm on a Platform with Multi-core Processors -- On the Difficulty...”
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Architecture of Computing Systems -- ARCS 2013 26th International Conference, Prague, Czech Republic, February 19-22, 2013 Proceedings /

Published 2013

Table of Contents: “... -- Power Monitoring for Mixed-Criticality on a Many-Core Platform -- On Confident Task-Accurate Performance...”
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Reconfigurable Computing: Architectures, Tools and Applications 6th International Symposium, ARC 2010, Bangkok, Thailand, March 17-19, 2010, Proceedings /

Published 2010

Table of Contents: “...Keynotes (Abstracts) -- High-Performance Energy-Efficient Reconfigurable Accelerators/Co-processors...”
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High Performance Computing for Computational Science - VECPAR 2008 8th International Conference, Toulouse, France, June 24-27, 2008. Revised Selected Papers /

Published 2008

Table of Contents: “... of Sparse LU Factorization and Triangular Solution on Multicore Platforms -- A Parallel Matrix Scaling...”
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