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Languages and Compilers for Parallel Computing 18th International Workshop, LCPC 2005, Hawthorne, NY, USA, October 20-22, 2005, Revised Selected Papers /

Published 2006

Table of Contents: “... Domain Specific Language on Network Processors -- Array Replication to Increase Parallelism...”
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Languages and Compilers for Parallel Computing 22nd International Workshop, LCPC 2009, Newark, DE, USA, October 8-10, 2009, Revised Selected Papers /

Published 2010

Table of Contents: “...A Communication Framework for Fault-Tolerant Parallel Execution -- The STAPL pList -- Hardware...”
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Algorithms and Architectures for Parallel Processing 10th International Conference, ICA3PP 2010, Busan, Korea, May 21-23, 2010. Proceedings, Part I /

Published 2010

Table of Contents: “... in Distributed Environments by Simultaneous Fragmentation and Allocation -- Parallel Architectures -- Function...”
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Multicore Systems On-Chip: Practical Software/Hardware Design

by Ben Abdallah, Abderazek., Ben Abdallah, Abderazek.
Published 2013

Table of Contents: “... NoCs -- Parallelizing Compiler for Single and Multicore Computing -- Power Optimization Techniques...”
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Turbo Decoder Architecture for Beyond-4G Applications

by Wong, Cheng-Chi., Wong, Cheng-Chi., Chang, Hsie-Chia.
Published 2014

Table of Contents: “...Introduction -- Conventional Architecture of Turbo Decoder -- Turbo Decoder with Parallel...”
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Embedded Computer Systems: Architectures, Modeling, and Simulation 6th International Workshop, SAMOS 2006, Samos, Greece, July 17-20, 2006, Proceedings /

Published 2006

Table of Contents: “... Spaces with Massively Parallel Embedded Processors -- Efficient Automated Clock Gating Using CoDeL...”
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High Performance Computational Science and Engineering IFIP TC5 Workshop on High Performance Computational Science and Engineering (HPCSE), World Computer Congress, August 22-27, 2...

Published 2005

Table of Contents: “... Zeros of Analytic Functions -- Reducing Overhead in Sparse Hypermatrix Cholesky Factorization...”
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High-Performance Computing 6th International Symposium, ISHPC 2005, Nara, Japan, September 7-9, 2005, First International Workshop on Advance Low Power Systems, ALPS 2006, Revised...

Published 2008

Table of Contents: “... Power -- Reducing Misspeculation Penalty in Trace-Level Speculative Multithreaded Architectures...”
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High Performance Embedded Architectures and Compilers Third International Conference, HiPEAC 2008, Göteborg, Sweden, January 27-29, 2008, Proceedings /

Published 2008

Table of Contents: “... Processors and Application Parallelization -- Compilation Strategies for Reducing Code Size on a VLIW...”
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Advances in Computer Systems Architecture 11th Asia-Pacific Conference, ACSAC 2006, Shanghai, China, September 6-8, 2006, Proceedings /

Published 2006

Table of Contents: “... for Programming Chip Multiprocessors -- Functional Unit Chaining: A Runtime Adaptive Architecture for Reducing...”
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Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation 17th International Workshop, PATMOS 2007, Gothenburg, Sweden, September 3-5, 2007, Proc...

Published 2007

Table of Contents: “... on the TTA -- Asynchronous Functional Coupling for Low Power Sensor Network Processors -- A Heuristic...”
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Transactions on High-Performance Embedded Architectures and Compilers IV

Published 2011

Table of Contents: “... Transactional Memory -- A Parallelizing Compiler Cooperative Heterogeneous Multicore Processor Architecture -- A...”
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Computer Science -- Theory and Applications First International Symposium on Computer Science in Russia, CSR 2006, St. Petersburg, Russia, June 8-12, 2006, Proceedings /

Published 2006

Table of Contents: “... of Asynchronous Automata -- Conjugacy and Equivalence of Weighted Automata and Functional Transducers...”
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Evolvable Systems: From Biology to Hardware 7th International Conference, ICES 2007, Wuhan, China, September 21-23, 2007, Proceedings /

Published 2007

Table of Contents: “... Cores to Evolve Combinational Logic Circuits in Parallel -- An Intrinsic Evolvable Hardware Based...”
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Architecture of Computing Systems -- ARCS 2013 26th International Conference, Prague, Czech Republic, February 19-22, 2013 Proceedings /

Published 2013

Table of Contents: “...: The Programming Model for Future Many-Core Processors -- A Highly Dependable Self-adaptive Mixed-Signal Multi-core...”
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Artificial Intelligence and Knowledge Engineering Applications: A Bioinspired Approach First International Work-Conference on the Interplay Between Natural and Artificial Computati...

Published 2005

Table of Contents: “... Rule-Table for Function Approximation by Use of Symbolic Regression in 1D and 2D Cases -- Parallel...”
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High Performance Computing Systems and Applications 23rd International Symposium, HPCS 2009, Kingston, Ontario, Canada, June 14-17, 2009, Revised Selected Papers /

Published 2010

Table of Contents: “... Mechanics -- A Hybrid Parallel Algorithm for Transforming Finite Element Functions from Adaptive...”
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Intelligent Data Engineering and Automated Learning -- IDEAL 2010 11th International Conference, Paisley, UK, September 1-3, 2010, Proceedings /

Published 2010

Table of Contents: “...Large Scale Instance Selection by Means of a Parallel Algorithm -- Typed Linear Chain Conditional...”
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Artificial Neural Networks - ICANN 2010 20th International Conference, Thessaloniki, Greece, September 15-18, 2010, Proceedings, Part III /

Published 2010

Table of Contents: “... Networks -- Local Minima of a Quadratic Binary Functional with a Quasi-Hebbian Connection Matrix -- A...”
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Applied Reconfigurable Computing 11th International Symposium, ARC 2015, Bochum, Germany, April 13-17, 2015, Proceedings /

Published 2015

Table of Contents: “...Architecture and Modeling -- Reducing Storage Costs of Reconfiguration Contexts by Sharing...”
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