Search Results - program array processor implementation https https*

1

Signal-to-noise ratio study on pipelined fast fourier transform processor

by Hassan, Siti Lailatul, Sulaiman, Nasri, Shariffudin, Shafinaz Sobihana, Tuan Yaakub, Tuan Norjihan
Published 2018

“... implemented on field-programable gate array (FPGA). This processor can be used in vast digital signal...”
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2

High Performance Embedded Architectures and Compilers Third International Conference, HiPEAC 2008, Göteborg, Sweden, January 27-29, 2008, Proceedings /

Published 2008

Table of Contents: “... Reconfigurable Array -- Implementation of an UWB Impulse-Radio Acquisition and Despreading Algorithm on a Low...”
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3

Reconfigurable Computing: Architectures and Applications Second International Workshop, ARC 2006, Delft, The Netherlands, March 1-3, 2006 Revised Selected Papers /

Published 2006

Table of Contents: “... -- Implementation of Inner Product Architecture for Increased Flexibility in Bitwidths of Input Array -- A Flexible...”
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4

Embedded Computer Systems: Architectures, Modeling, and Simulation 6th International Workshop, SAMOS 2006, Samos, Greece, July 17-20, 2006, Proceedings /

Published 2006

Table of Contents: “... Processors -- SAD Prefetching for MPEG4 Using Flux Caches -- Effects of Program Compression -- Integrated...”
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5

Embedded Computer Systems: Architectures, Modeling, and Simulation 8th International Workshop, SAMOS 2008, Samos, Greece, July 21-24, 2008, Proceedings /

Published 2008

Table of Contents: “... -- to Programming Multicores -- Design Issues in Parallel Array Languages for Shared Memory -- An Architecture...”
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6

Embedded Computer Systems: Architectures, Modeling, and Simulation 5th International Workshop, SAMOS 2005, Samos, Greece, July 18-20, Proceedings /

Published 2005

Table of Contents: “... Multiple Operation Array -- RAPANUI: Rapid Prototyping for Media Processor Architecture Exploration -- Data...”
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7

Parallel Computing Technologies 9th International Conference, PaCT 2007, Pereslavl-Zalessky, Russia, September 3-7, 2007, Proceedings /

Published 2007

Table of Contents: “... and Consensus -- A Functional Programming System SFP: Sisal 3.1 Language Structures Decomposition -- Towards a...”
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8

Embedded Computer Systems: Architectures, Modeling, and Simulation 7th International Workshop, SAMOS 2007, Samos, Greece, July 16-19, 2007, Proceedings /

Published 2007

Table of Contents: “... and Programming Model -- Multi-processor Architectures -- Mapping and Performance Evaluation for Heterogeneous MP...”
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9

Three-Dimensional Design Methodologies for Tree-based FPGA Architecture

by Pangracious, Vinod., Pangracious, Vinod., Marrakchi, Zied., Mehrez, Habib.
Published 2015

Table of Contents: “... Than Moore Technology -- Field Programmable Gate Arrays: An Overview -- Two Dimensional FPGAs...”
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10

Algorithms and Architectures for Parallel Processing 10th International Conference, ICA3PP 2010, Busan, Korea, May 21-23, 2010. Proceedings, Part I /

Published 2010

Table of Contents: “... Algorithm for Chip Multiprocessor -- Efficient Partitioning of Static Buses for Processor Arrays of Small...”
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VLSI-SoC: From Algorithms to Circuits and System-on-Chip Design 20th IFIP WG 10.5/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2012, Santa Cruz, CA, USA,...

Published 2013

Table of Contents: “... Programs for Functional Test and Diagnosis of VLIW Processors -- SEU-Aware Low-Power Memories Using a...”
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12

DSP Architecture Design Essentials

by Marković, Dejan., Marković, Dejan., Brodersen, Robert W.
Published 2012

Table of Contents: “...-rate Neural Processors -- Brief Outlook....”
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13

High Performance Computing – HiPC 2005 12th International Conference, Goa, India, December 18-21, 2005, Proceedings /

Published 2005

Table of Contents: “... to Network Processor for Parallel Query Processing in Cluster of Workstations -- A High-Speed VLSI Array...”
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14

Languages and Compilers for High Performance Computing 17th International Workshop, LCPC 2004, West Lafayette, IN, USA, September 22-24, 2004, Revised Selected Papers /

Published 2005

Table of Contents: “... -- Implementation of Parallel Numerical Algorithms Using Hierarchically Tiled Arrays -- A Geometric Approach...”
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15

Evolvable Systems: From Biology to Hardware 7th International Conference, ICES 2007, Wuhan, China, September 21-23, 2007, Proceedings /

Published 2007

Table of Contents: “... Classification -- Design of Electronic Circuits Using a Divide-and-Conquer Approach -- Implementing Multi-VRC...”
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16

Architecture of Computing Systems - ARCS 2008 21st International Conference, Dresden, Germany, February 25-28, 2008, Proceedings /

Published 2008

Table of Contents: “... Computer Architecture -- A Generic Network Interface Architecture for a Networked Processor Array (NePA...”
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17

Reconfigurable Computing: Architectures, Tools and Applications 6th International Symposium, ARC 2010, Bangkok, Thailand, March 17-19, 2010, Proceedings /

Published 2010

Table of Contents: “... Processor -- FPGA Implementation of QR Decomposition Using MGS Algorithm -- Memory-Centric Communication...”
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18

Handbook of Signal Processing Systems

Published 2010

Table of Contents: “... -- General-Purpose DSP Processors -- Application Specific Instruction Set DSP Processors -- Coarse-Grained...”
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19

Architecture of Computing Systems - ARCS 2006 19th International Conference, Frankfurt/Main, Germany, March 13-16, 2006, Proceedings /

Published 2006

Table of Contents: “... Rendering -- Architectures -- Controller Synthesis for Mapping Partitioned Programs on Array Architectures...”
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20

Parallel Processing and Applied Mathematics, Part II 8th International Conference, PPAM 2009, Wroclaw, Poland, September 13-16, 2009, Proceedings /

Published 2010

Table of Contents: “... -- Fast Multi-objective Reschulding of Grid Jobs by Heuristics and Evolution -- Comparison of Program Task...”
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