Search Results - programming functional processes processor array http

1

Digital Signal Processor (DSP) Design Using Very Long Instruction Word (VLIW) Architecture

by Lee, Lini @ Lini Lee
Published 2001

“... Processor) core. The architecture of the pDSP core must be designed in such a way that parallel processing...”
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Thesis

2

Digital Signal Processor (DSP) Design Using Very Long Instruction Word (VLIW) Architecture

by Lee, Lini @ Lini Lee
Published 2001

“... Processor) core. The architecture of the pDSP core must be designed in such a way that parallel processing...”
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Thesis

3

Algorithms and Architectures for Parallel Processing 10th International Conference, ICA3PP 2010, Busan, Korea, May 21-23, 2010. Proceedings, Part I /

Published 2010

Table of Contents: “... Algorithm for Chip Multiprocessor -- Efficient Partitioning of Static Buses for Processor Arrays of Small...”
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4

Parallel Processing and Applied Mathematics, Part II 8th International Conference, PPAM 2009, Wroclaw, Poland, September 13-16, 2009, Proceedings /

Published 2010

Table of Contents: “... -- Fast Multi-objective Reschulding of Grid Jobs by Heuristics and Evolution -- Comparison of Program Task...”
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Electronic eBook

5

Low power multicarrier- code division multiple access receiver on field programmable gate array

by Mohd Hassan, Siti Lailatul, Sulaiman, Nasri, Saparon, Azilah, Mohd Yussoff, Yusnani, Jaafar, Haslina
Published 2019

“... on field-programable gate array (FPGA). Most of the wireless application nowadays such as wireless sensor...”
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Article

6

High Performance Embedded Architectures and Compilers Third International Conference, HiPEAC 2008, Göteborg, Sweden, January 27-29, 2008, Proceedings /

Published 2008

Table of Contents: “... Processing -- rMPI: Message Passing on Multicore Processors with On-Chip Interconnect -- Modeling Multigrain...”
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7

Reconfigurable Computing: Architectures, Tools and Applications 6th International Symposium, ARC 2010, Bangkok, Thailand, March 17-19, 2010, Proceedings /

Published 2010

Table of Contents: “...Keynotes (Abstracts) -- High-Performance Energy-Efficient Reconfigurable Accelerators/Co-processors...”
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8

Computer Aided Systems Theory – EUROCAST 2005 10th International Conference on Computer Aided Systems Theory, Las Palmas de Gran Canaria, Spain, February 7-11, 2005, Revised Select...

Published 2005

Table of Contents: “... Through Span Composition -- Degenerate Arrays: A Framework for Uncertain Data Tables -- Neural Network...”
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9

Embedded Computer Systems: Architectures, Modeling, and Simulation 6th International Workshop, SAMOS 2006, Samos, Greece, July 17-20, 2006, Proceedings /

Published 2006

Table of Contents: “... Processors -- SAD Prefetching for MPEG4 Using Flux Caches -- Effects of Program Compression -- Integrated...”
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10

Embedded Computer Systems: Architectures, Modeling, and Simulation 8th International Workshop, SAMOS 2008, Samos, Greece, July 21-24, 2008, Proceedings /

Published 2008

Table of Contents: “... -- to Programming Multicores -- Design Issues in Parallel Array Languages for Shared Memory -- An Architecture...”
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11

Embedded Computer Systems: Architectures, Modeling, and Simulation 5th International Workshop, SAMOS 2005, Samos, Greece, July 18-20, Proceedings /

Published 2005

Table of Contents: “... Multiple Operation Array -- RAPANUI: Rapid Prototyping for Media Processor Architecture Exploration -- Data...”
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12

Embedded Computer Systems: Architectures, Modeling, and Simulation 7th International Workshop, SAMOS 2007, Samos, Greece, July 16-19, 2007, Proceedings /

Published 2007

Table of Contents: “... and Programming Model -- Multi-processor Architectures -- Mapping and Performance Evaluation for Heterogeneous MP...”
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Electronic eBook

13

Large-Scale Scientific Computing 8th International Conference, LSSC 2011, Sozopol, Bulgaria, June 6-10th, 2011. Revised Selected Papers /

Published 2012

Table of Contents: “... and Applications to Aerodynamics .-Processor Array Design with the Use of Genetic Algorithm.-A Hybrid Genetic...”
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14

High Performance Computing - HiPC 2008 15th International Conference, Bangalore, India, December 17-20, 2008, Proceedings /

Published 2008

Table of Contents: “... Performance of Digest Caches in Network Processors -- Optimization of BLAS on the Cell Processor -- Fine...”
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15

Artificial Evolution 9th International Conference, Evolution Artificielle, EA 2009, Strasbourg, France, October 26-28, 2009. Revised Selected Papers /

Published 2010

Table of Contents: “... -- Parallelization of an Evolutionary Algorithm on a Platform with Multi-core Processors -- On the Difficulty...”
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16

Network and Parallel Computing IFIP International Conference, NPC 2005, Beijing, China, November 30 - December 3, 2005, Proceedings /

Published 2005

Table of Contents: “... Programming and Environment -- A Greedy Algorithm for Capacity-Constrained Surrogate Placement in CDNs...”
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17

VLSI-SoC: From Algorithms to Circuits and System-on-Chip Design 20th IFIP WG 10.5/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2012, Santa Cruz, CA, USA,...

Published 2013

Table of Contents: “... Programs for Functional Test and Diagnosis of VLIW Processors -- SEU-Aware Low-Power Memories Using a...”
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18

Embedded System Design: Topics, Techniques and Trends IFIP TC10 Working Conference: International Embedded Systems Symposium (IESS), May 30 - June 1, 2007, Irvine (CA), USA /

Published 2007

Table of Contents: “...-Processor Systems with Static Priorities -- Approach for a Formal Verification of a Bit-serial Pipelined...”
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