Search Results - programming microprocessor data processor array https

1

Guide to Assembly Language A Concise Introduction /

by Streib, James T., Streib, James T.
Published 2011

Table of Contents: “...Variables, Registers, and Data Movement -- Input/Output -- Arithmetic Instructions -- Selection...”
View full text

Electronic eBook

2

High Performance Embedded Architectures and Compilers 5th International Conference, HiPEAC 2010, Pisa, Italy, January 25-27, 2010, Proceedings /

Published 2010

Table of Contents: “... Penalty -- Trace-Based Data Layout Optimizations for Multi-core Processors -- Buffer Sizing for Self-timed...”
View full text

Electronic eBook

3

High Performance Embedded Architectures and Compilers Third International Conference, HiPEAC 2008, Göteborg, Sweden, January 27-29, 2008, Proceedings /

Published 2008

Table of Contents: “... Processor with Variable Length Instructions -- Experiences with Parallelizing a Bio-informatics Program...”
View full text

Electronic eBook

4

Handbook of Signal Processing Systems

Published 2010

Table of Contents: “... -- General-Purpose DSP Processors -- Application Specific Instruction Set DSP Processors -- Coarse-Grained...”
View full text

Electronic eBook

5

DSP Architecture Design Essentials

by Marković, Dejan., Marković, Dejan., Brodersen, Robert W.
Published 2012

Table of Contents: “... Analysis -- Data-Flow Graph Model -- Wordlength Optimization -- Architectural Optimization -- Simulink...”
View full text

Electronic eBook

6

High Performance Computing – HiPC 2005 12th International Conference, Goa, India, December 18-21, 2005, Proceedings /

Published 2005

Table of Contents: “... to Network Processor for Parallel Query Processing in Cluster of Workstations -- A High-Speed VLSI Array...”
View full text

Electronic eBook

7

Computer Aided Systems Theory – EUROCAST 2005 10th International Conference on Computer Aided Systems Theory, Las Palmas de Gran Canaria, Spain, February 7-11, 2005, Revised Select...

Published 2005

Table of Contents: “... Through Span Composition -- Degenerate Arrays: A Framework for Uncertain Data Tables -- Neural Network...”
View full text

Electronic eBook

8

Reconfigurable Computing: Architectures and Applications Second International Workshop, ARC 2006, Delft, The Netherlands, March 1-3, 2006 Revised Selected Papers /

Published 2006

Table of Contents: “... Processor with Partial Predication and Virtual Opcode Support -- A Reconfigurable Data Cache for Adaptive...”
View full text

Electronic eBook

9

Embedded Computer Systems: Architectures, Modeling, and Simulation 6th International Workshop, SAMOS 2006, Samos, Greece, July 17-20, 2006, Proceedings /

Published 2006

Table of Contents: “... Processors -- SAD Prefetching for MPEG4 Using Flux Caches -- Effects of Program Compression -- Integrated...”
View full text

Electronic eBook

10

Embedded Computer Systems: Architectures, Modeling, and Simulation 8th International Workshop, SAMOS 2008, Samos, Greece, July 21-24, 2008, Proceedings /

Published 2008

Table of Contents: “... -- to Programming Multicores -- Design Issues in Parallel Array Languages for Shared Memory -- An Architecture...”
View full text

Electronic eBook

11

Embedded Computer Systems: Architectures, Modeling, and Simulation 5th International Workshop, SAMOS 2005, Samos, Greece, July 18-20, Proceedings /

Published 2005

Table of Contents: “... Multiple Operation Array -- RAPANUI: Rapid Prototyping for Media Processor Architecture Exploration -- Data...”
View full text

Electronic eBook

12

High Performance Computing - HiPC 2004 11th International Conference, Bangalore, India, December 19-22, 2004, Proceedings /

Published 2005

Table of Contents: “... and Heterogeneous Processor Rings -- Effect of Optimizations on Performance of OpenMP Programs -- Sparse Matrices...”
View full text

Electronic eBook

13

Architecture of Computing Systems - ARCS 2006 19th International Conference, Frankfurt/Main, Germany, March 13-16, 2006, Proceedings /

Published 2006

Table of Contents: “... Rendering -- Architectures -- Controller Synthesis for Mapping Partitioned Programs on Array Architectures...”
View full text

Electronic eBook

14

Embedded System Design: Topics, Techniques and Trends IFIP TC10 Working Conference: International Embedded Systems Symposium (IESS), May 30 - June 1, 2007, Irvine (CA), USA /

Published 2007

Table of Contents: “... -- Hardware Synthesis -- Automatic Data Path Generation from C code for Custom Processors -- Interconnect...”
View full text

Electronic eBook

Narrow Search