Resultados de procura - programming optimization process processor array http

1

Digital Signal Processor (DSP) Design Using Very Long Instruction Word (VLIW) Architecture

por Lee, Lini @ Lini Lee
Publicado 2001

“... Processor) core. The architecture of the pDSP core must be designed in such a way that parallel processing...”
Ligazón do recurso

Thesis

2

Digital Signal Processor (DSP) Design Using Very Long Instruction Word (VLIW) Architecture

por Lee, Lini @ Lini Lee
Publicado 2001

“... Processor) core. The architecture of the pDSP core must be designed in such a way that parallel processing...”
Ligazón do recurso

Thesis

3

Handbook of Signal Processing Systems

Publicado 2010

Table of Contents: “... Arrays -- Decidable Signal Processing Dataflow Graphs: Synchronous and Cyclo-Static Dataflow Graphs...”
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Electrónico eBook

4

Algorithms and Architectures for Parallel Processing 10th International Conference, ICA3PP 2010, Busan, Korea, May 21-23, 2010. Proceedings, Part I /

Publicado 2010

Table of Contents: “... with Graphic Processing Unit -- Optimizing Sweep3D for Graphic Processor Unit -- Modular Resultant Algorithm...”
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Electrónico eBook

5

Parallel Processing and Applied Mathematics, Part II 8th International Conference, PPAM 2009, Wroclaw, Poland, September 13-16, 2009, Proceedings /

Publicado 2010

Table of Contents: “... -- Fast Multi-objective Reschulding of Grid Jobs by Heuristics and Evolution -- Comparison of Program Task...”
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Electrónico eBook

6

String Processing and Information Retrieval 20th International Symposium, SPIRE 2013, Jerusalem, Israel, October 7-9, 2013, Proceedings /

Publicado 2013

Table of Contents: “... Engine Processors -- Query Processing in Highly-Loaded Search Engines -- Indexes for Jumbled Pattern...”
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Electrónico eBook

7

DSP Architecture Design Essentials

por Marković, Dejan., Marković, Dejan., Brodersen, Robert W.
Publicado 2012

Table of Contents: “...Energy and Delay Models -- Circuit Optimization -- Architectural Techniques -- Architecture...”
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Electrónico eBook

8

High Performance Embedded Architectures and Compilers Third International Conference, HiPEAC 2008, Göteborg, Sweden, January 27-29, 2008, Proceedings /

Publicado 2008

Table of Contents: “... Processing -- rMPI: Message Passing on Multicore Processors with On-Chip Interconnect -- Modeling Multigrain...”
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Electrónico eBook

9

High Performance Computing – HiPC 2005 12th International Conference, Goa, India, December 18-21, 2005, Proceedings /

Publicado 2005

Table of Contents: “... to Network Processor for Parallel Query Processing in Cluster of Workstations -- A High-Speed VLSI Array...”
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Electrónico eBook

10

Reconfigurable Computing: Architectures, Tools and Applications 6th International Symposium, ARC 2010, Bangkok, Thailand, March 17-19, 2010, Proceedings /

Publicado 2010

Table of Contents: “...Keynotes (Abstracts) -- High-Performance Energy-Efficient Reconfigurable Accelerators/Co-processors...”
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Electrónico eBook

11

Computer Aided Systems Theory – EUROCAST 2005 10th International Conference on Computer Aided Systems Theory, Las Palmas de Gran Canaria, Spain, February 7-11, 2005, Revised Select...

Publicado 2005

Table of Contents: “... Through Span Composition -- Degenerate Arrays: A Framework for Uncertain Data Tables -- Neural Network...”
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Electrónico eBook

12

Reconfigurable Computing: Architectures and Applications Second International Workshop, ARC 2006, Delft, The Netherlands, March 1-3, 2006 Revised Selected Papers /

Publicado 2006

Table of Contents: “...-Embedded Processors -- Dynamic Partial Reconfigurable FIR Filter Design -- Event-Driven Simulation Engine...”
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Electrónico eBook

13

Embedded Computer Systems: Architectures, Modeling, and Simulation 6th International Workshop, SAMOS 2006, Samos, Greece, July 17-20, 2006, Proceedings /

Publicado 2006

Table of Contents: “... -- An Optimization Methodology for Memory Allocation and Task Scheduling in SoCs Via Linear Programming -- Wireless...”
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Electrónico eBook

14

Large-Scale Scientific Computing 8th International Conference, LSSC 2011, Sozopol, Bulgaria, June 6-10th, 2011. Revised Selected Papers /

Publicado 2012

Table of Contents: “... and Applications to Aerodynamics .-Processor Array Design with the Use of Genetic Algorithm.-A Hybrid Genetic...”
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Electrónico eBook

15

Embedded Computer Systems: Architectures, Modeling, and Simulation 5th International Workshop, SAMOS 2005, Samos, Greece, July 18-20, Proceedings /

Publicado 2005

Table of Contents: “... Multiple Operation Array -- RAPANUI: Rapid Prototyping for Media Processor Architecture Exploration -- Data...”
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16

Embedded Computer Systems: Architectures, Modeling, and Simulation 7th International Workshop, SAMOS 2007, Samos, Greece, July 16-19, 2007, Proceedings /

Publicado 2007

Table of Contents: “... and Programming Model -- Multi-processor Architectures -- Mapping and Performance Evaluation for Heterogeneous MP...”
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Electrónico eBook

17

High Performance Computing - HiPC 2004 11th International Conference, Bangalore, India, December 19-22, 2004, Proceedings /

Publicado 2005

Table of Contents: “... and Heterogeneous Processor Rings -- Effect of Optimizations on Performance of OpenMP Programs -- Sparse Matrices...”
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Electrónico eBook

18

High Performance Computing - HiPC 2008 15th International Conference, Bangalore, India, December 17-20, 2008, Proceedings /

Publicado 2008

Table of Contents: “... Performance of Digest Caches in Network Processors -- Optimization of BLAS on the Cell Processor -- Fine...”
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Electrónico eBook

19

High Performance Computing and Communications Third International Conference, HPCC 2007, Houston, USA, September 26-28, 2007, Proceedings /

Publicado 2007

Table of Contents: “... -- Strategies and Implementation for Translating OpenMP Code for Clusters -- Optimizing Array Accesses in High...”
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Electrónico eBook

20

Artificial Evolution 9th International Conference, Evolution Artificielle, EA 2009, Strasbourg, France, October 26-28, 2009. Revised Selected Papers /

Publicado 2010

Table of Contents: “... -- Combinatorial Optimization -- Memetic Algorithms for Constructing Binary Covering Arrays of Strength Three -- A...”
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Electrónico eBook

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