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Handbook of Signal Processing Systems

Published 2010

Table of Contents: “... and Tools for Mapping Process Networks onto Multi-Processor Systems-On-Chip -- Integrated Modeling using...”
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Algorithms and Architectures for Parallel Processing 10th International Conference, ICA3PP 2010, Busan, Korea, May 21-23, 2010. Proceedings, Part I /

Published 2010

Table of Contents: “... Algorithm for Chip Multiprocessor -- Efficient Partitioning of Static Buses for Processor Arrays of Small...”
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Design Concepts for a Virtualizable Embedded MPSoC Architecture Enabling Virtualization in Embedded Multi-Processor Systems /

by Biedermann, Alexander., Biedermann, Alexander.
Published 2014

Subjects: “...Software Engineering/Programming and Operating Systems. https://scigraph.springernature.com...”
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Digital Signal Processor (DSP) Design Using Very Long Instruction Word (VLIW) Architecture

by Lee, Lini @ Lini Lee
Published 2001

“... Processor) core. The architecture of the pDSP core must be designed in such a way that parallel processing...”
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Thesis

Digital Signal Processor (DSP) Design Using Very Long Instruction Word (VLIW) Architecture

by Lee, Lini @ Lini Lee
Published 2001

“... Processor) core. The architecture of the pDSP core must be designed in such a way that parallel processing...”
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Thesis

VLSI-SoC: From Algorithms to Circuits and System-on-Chip Design 20th IFIP WG 10.5/IEEE...

Published 2013

Table of Contents: “... Programs for Functional Test and Diagnosis of VLIW Processors -- SEU-Aware Low-Power Memories Using a...”
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Digital signal processor (DSP) design using very long instruction word (VLIW) architecture /

by Lee, Lini @ Lini Lee.

Thesis Book

High Performance Embedded Architectures and Compilers Third International Conference, HiPEAC 2008, Göteborg, Sweden, January 27-29, 2008, Proceedings /

Published 2008

Table of Contents: “... Processing -- rMPI: Message Passing on Multicore Processors with On-Chip Interconnect -- Modeling Multigrain...”
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High Performance Computing – HiPC 2005 12th International Conference, Goa, India, December 18-21, 2005, Proceedings /

Published 2005

Table of Contents: “... to Network Processor for Parallel Query Processing in Cluster of Workstations -- A High-Speed VLSI Array...”
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Reconfigurable Computing: Architectures, Tools and Applications 6th International Symposium, ARC 2010, Bangkok, Thailand, March 17-19, 2010, Proceedings /

Published 2010

Table of Contents: “...Keynotes (Abstracts) -- High-Performance Energy-Efficient Reconfigurable Accelerators/Co-processors...”
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Reconfigurable Computing: Architectures and Applications Second International Workshop, ARC 2006, Delft, The Netherlands, March 1-3, 2006 Revised Selected Papers /

Published 2006

Table of Contents: “...-Embedded Processors -- Dynamic Partial Reconfigurable FIR Filter Design -- Event-Driven Simulation Engine...”
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Embedded Computer Systems: Architectures, Modeling, and Simulation 7th International Workshop, SAMOS 2007, Samos, Greece, July 16-19, 2007, Proceedings /

Published 2007

Table of Contents: “... and Programming Model -- Multi-processor Architectures -- Mapping and Performance Evaluation for Heterogeneous MP...”
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Embedded Computer Systems: Architectures, Modeling, and Simulation 5th International Workshop, SAMOS 2005, Samos, Greece, July 18-20, Proceedings /

Published 2005

Table of Contents: “... Multiple Operation Array -- RAPANUI: Rapid Prototyping for Media Processor Architecture Exploration -- Data...”
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Embedded Computer Systems: Architectures, Modeling, and Simulation 8th International Workshop, SAMOS 2008, Samos, Greece, July 21-24, 2008, Proceedings /

Published 2008

Table of Contents: “... -- to Programming Multicores -- Design Issues in Parallel Array Languages for Shared Memory -- An Architecture...”
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Embedded System Design: Topics, Techniques and Trends IFIP TC10 Working Conference: International Embedded Systems Symposium (IESS), May 30 - June 1, 2007, Irvine (CA), USA /

Published 2007

Table of Contents: “...-Processor Systems with Static Priorities -- Approach for a Formal Verification of a Bit-serial Pipelined...”
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