Search Results - programming processors programming processor array http

1

Cellular automation for efficient impulse noise removal and edge detection using graphic processor unit

by Jalalian, Afsaneh
Published 2010

Subjects: “...Parallel programming (Computer science)...”
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Thesis

2

Fast fourier transform processor implementation for high inputs on field programmable gates array

by Ali Abbas, Zaid
Published 2018

“..., hardware resources usage and speed for radix-(2, 4 and 8) FFT processor, using the same device...”
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Thesis

3

Fast fourier transform processor implementation for high inputs on field programmable gates array

by Ali Abbas, Zaid
Published 2018

“... usage and speed for radix-(2, 4 and 8) FFT processor, using the same device and environment...”
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Thesis

4

Design and implementation of real data fast fourier transform processor on field programmable gates array

by Ahmed, Mohammed Kassim
Published 2015

Subjects: “...Field programmable gate arrays...”
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Thesis

5

Design and implementation of real data fast fourier transform processor on field programmable gates array

by Ahmed, Mohammed Kassim
Published 2015

“... algorithm is implemented on Cyclone II Field Programmable Gates Array (FPGA). In order to program the FPGA...”
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Thesis

6

Signal-to-noise ratio study on pipelined fast fourier transform processor

by Hassan, Siti Lailatul, Sulaiman, Nasri, Shariffudin, Shafinaz Sobihana, Tuan Yaakub, Tuan Norjihan
Published 2018

“... implemented on field-programable gate array (FPGA). This processor can be used in vast digital signal...”
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Article

7

Guide to Assembly Language A Concise Introduction /

by Streib, James T., Streib, James T.
Published 2011

Table of Contents: “... -- Arrays -- Strings -- Selected Machine Language Instructions....”
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Electronic eBook

8

Cellular automation for efficient impulse noise removal and edge detection using graphic processor unit

by Jalalian, Afsaneh
Published 2010

“... such as the Graphic Processor Unit and Field Programmable Gate Array. In recent years the tendency to use of cellular...”
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Thesis

9

Digital Signal Processor (DSP) Design Using Very Long Instruction Word (VLIW) Architecture

by Lee, Lini @ Lini Lee
Published 2001

“...Programmable digital signal processors (pDSP) are microprocessors that are specialized to perform...”
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Thesis

10

Digital Signal Processor (DSP) Design Using Very Long Instruction Word (VLIW) Architecture

by Lee, Lini @ Lini Lee
Published 2001

“...Programmable digital signal processors (pDSP) are microprocessors that are specialized to perform...”
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Thesis

11

Design Concepts for a Virtualizable Embedded MPSoC Architecture Enabling Virtualization in Embedded Multi-Processor Systems /

by Biedermann, Alexander., Biedermann, Alexander.
Published 2014

Subjects: “...Software Engineering/Programming and Operating Systems. https://scigraph.springernature.com...”
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Electronic eBook

12

Quantum Processing Framework And Hybrid Algorithms For Routing Problems

by Soltan Aghaei, Mohammad Reza
Published 2010

Subjects: “...Hybrid computers - Programming....”
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Thesis

13

Hardware/Software Co-design for Heterogeneous Multi-core Platforms The hArtes Toolchain /

Published 2012

Table of Contents: “...Introduction -- ThArtes Toolchain -- The hArtes Platform -- Audio Array Processing for Telepresence...”
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Electronic eBook

14

Low power multicarrier- code division multiple access receiver on field programmable gate array

by Mohd Hassan, Siti Lailatul, Sulaiman, Nasri, Saparon, Azilah, Mohd Yussoff, Yusnani, Jaafar, Haslina
Published 2019

“... on field-programable gate array (FPGA). Most of the wireless application nowadays such as wireless sensor...”
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Article

15

High Performance Embedded Architectures and Compilers 5th International Conference, HiPEAC 2010, Pisa, Italy, January 25-27, 2010, Proceedings /

Published 2010

Table of Contents: “... Strategy for Network Processors -- Memory-Aware Application Mapping on Coarse-Grained Reconfigurable Arrays...”
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Electronic eBook

16

High Performance Embedded Architectures and Compilers Third International Conference, HiPEAC 2008, Göteborg, Sweden, January 27-29, 2008, Proceedings /

Published 2008

Table of Contents: “... Processor with Variable Length Instructions -- Experiences with Parallelizing a Bio-informatics Program...”
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Electronic eBook

17

Three-Dimensional Design Methodologies for Tree-based FPGA Architecture

by Pangracious, Vinod., Pangracious, Vinod., Marrakchi, Zied., Mehrez, Habib.
Published 2015

Table of Contents: “... Than Moore Technology -- Field Programmable Gate Arrays: An Overview -- Two Dimensional FPGAs...”
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Electronic eBook

18

Languages and Compilers for Parallel Computing 18th International Workshop, LCPC 2005, Hawthorne, NY, USA, October 20-22, 2005, Revised Selected Papers /

Published 2006

Table of Contents: “... Domain Specific Language on Network Processors -- Array Replication to Increase Parallelism...”
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Electronic eBook

19

Languages and Compilers for High Performance Computing 17th International Workshop, LCPC 2004, West Lafayette, IN, USA, September 22-24, 2004, Revised Selected Papers /

Published 2005

Table of Contents: “... SPEC2000FP Benchmarks -- An Offline Approach for Whole-Program Paths Analysis Using Suffix Arrays...”
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Electronic eBook

20

Languages and Compilers for Parallel Computing 19th International Workshop, LCPC 2006, New Orleans, LA, USA, November 2-4, 2006, Revised Papers /

Published 2007

Table of Contents: “... for Hierarchically Tiled Arrays -- SP@CE - An SP-Based Programming Model for Consumer Electronics Streaming...”
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Electronic eBook

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