Cover Image

High-Level Verification Methods and Tools for Verification of System-Level Designs /

This book looks at the problem of design verification with a view towards speeding up the process of verification by developing methods that apply to levels of abstraction above RTL or synchronous logic descriptions. Typically such descriptions capture design functionality at the system level, hence...

Full description

Saved in:
Bibliographic Details
Main Authors: Kundu, Sudipta. (Author, http://id.loc.gov/vocabulary/relators/aut), Lerner, Sorin. (http://id.loc.gov/vocabulary/relators/aut), Gupta, Rajesh K. (http://id.loc.gov/vocabulary/relators/aut)
Corporate Author: SpringerLink (Online service)
Format: Electronic eBook
Language:English
Published: New York, NY : Springer New York : Imprint: Springer, 2011.
Edition:1st ed. 2011.
Subjects:
Electronic circuits.
Computer-aided engineering.
Circuits and Systems.
Computer-Aided Engineering (CAD, CAE) and Design.
Online Access:https://doi.org/10.1007/978-1-4419-9359-5
Tags: Add Tag
No Tags, Be the first to tag this record!

Internet

https://doi.org/10.1007/978-1-4419-9359-5

Similar Items