High-Level Verification Methods and Tools for Verification of System-Level Designs /
This book looks at the problem of design verification with a view towards speeding up the process of verification by developing methods that apply to levels of abstraction above RTL or synchronous logic descriptions. Typically such descriptions capture design functionality at the system level, hence...
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| Main Authors: | , , |
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| Korporativna značnica: | |
| Format: | Elektronski eKnjiga |
| Jezik: | English |
| Izdano: |
New York, NY :
Springer New York : Imprint: Springer,
2011.
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| Izdaja: | 1st ed. 2011. |
| Teme: | |
| Online dostop: | https://doi.org/10.1007/978-1-4419-9359-5 |
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Kazalo:
- Introduction
- Related Work
- Background
- Execution-based Model Checking for High-Level Designs
- Efficient Symbolic Analysis for Concurrent Programs
- Translation Validation of High-Level Synthesis
- Parameterized Program Equivalence Checking
- Conclusions and Future Work.