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A Pipelined Multi-core MIPS Machine Hardware Implementation and Correctness Proof /

This monograph is based on the third author's lectures on computer architecture, given in the summer semester 2013 at Saarland University, Germany. It contains a gate level construction of a multi-core machine with pipelined MIPS processor cores and a sequentially consistent shared memory. The...

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Autors principals: Kovalev, Mikhail. (Autor, http://id.loc.gov/vocabulary/relators/aut), Müller, Silvia M. (http://id.loc.gov/vocabulary/relators/aut), Paul, Wolfgang J. (http://id.loc.gov/vocabulary/relators/aut)
Autor corporatiu: SpringerLink (Online service)
Format: Electrònic eBook
Idioma:English
Publicat: Cham : Springer International Publishing : Imprint: Springer, 2014.
Edició:1st ed. 2014.
Periòdiques:Theoretical Computer Science and General Issues ; 9000
Matèries:
Algorithms.
Software engineering.
Computer hardware.
Microprocessors.
Computer communication systems.
Programming languages (Electronic computers).
Algorithm Analysis and Problem Complexity.
Software Engineering.
Computer Hardware.
Processor Architectures.
Computer Communication Networks.
Programming Languages, Compilers, Interpreters.
Accés en línia:https://doi.org/10.1007/978-3-319-13906-7
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https://doi.org/10.1007/978-3-319-13906-7

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