A Pipelined Multi-core MIPS Machine Hardware Implementation and Correctness Proof /
This monograph is based on the third author's lectures on computer architecture, given in the summer semester 2013 at Saarland University, Germany. It contains a gate level construction of a multi-core machine with pipelined MIPS processor cores and a sequentially consistent shared memory. The...
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| Hlavní autoři: | , , |
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| Korporativní autor: | |
| Médium: | Elektronický zdroj E-kniha |
| Jazyk: | English |
| Vydáno: |
Cham :
Springer International Publishing : Imprint: Springer,
2014.
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| Vydání: | 1st ed. 2014. |
| Edice: | Theoretical Computer Science and General Issues ;
9000 |
| Témata: | |
| On-line přístup: | https://doi.org/10.1007/978-3-319-13906-7 |
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