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High Performance Embedded Architectures and Compilers Second International Conference, HiPEAC 2007, Ghent, Belgium, January 28-30, 2007. Proceedings /

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Sonraí Bibleagrafaíochta
Údar Corparáideach: SpringerLink (Online service)
Údair Eile: De Bosschere, Koen. (Eagarthóir, http://id.loc.gov/vocabulary/relators/edt), Kaeli, David. (Eagarthóir, http://id.loc.gov/vocabulary/relators/edt), Stenström, Per. (Eagarthóir, http://id.loc.gov/vocabulary/relators/edt), Whalley, David. (Eagarthóir, http://id.loc.gov/vocabulary/relators/edt), Ungerer, Theo. (Eagarthóir, http://id.loc.gov/vocabulary/relators/edt)
Formáid: Leictreonach ríomhLeabhar
Teanga:English
Foilsithe: Berlin, Heidelberg : Springer Berlin Heidelberg : Imprint: Springer, 2007.
Eagrán:1st ed. 2007.
Sraith:Theoretical Computer Science and General Issues ; 4367
Ábhair:
Computers.
Arithmetic and logic units, Computer.
Microprocessors.
Input-output equipment (Computers).
Logic design.
Computer communication systems.
Theory of Computation.
Arithmetic and Logic Structures.
Processor Architectures.
Input/Output and Data Communications.
Logic Design.
Computer Communication Networks.
Rochtain Ar Líne:https://doi.org/10.1007/978-3-540-69338-3
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Clár Ábhair:
  • Invited Program
  • Keynote: Insight, Not (Random) Numbers: An Embedded Perspective
  • I Secure and Low-Power Embedded Memory Systems
  • Compiler-Assisted Memory Encryption for Embedded Processors
  • Leveraging High Performance Data Cache Techniques to Save Power in Embedded Systems
  • Applying Decay to Reduce Dynamic Power in Set-Associative Caches
  • II Architecture/Compiler Optimizations for Efficient Embedded Processing
  • Virtual Registers: Reducing Register Pressure Without Enlarging the Register File
  • Bounds Checking with Taint-Based Analysis
  • Reducing Exit Stub Memory Consumption in Code Caches
  • III Adaptive Microarchitectures
  • Reducing Branch Misprediction Penalties Via Adaptive Pipeline Scaling
  • Fetch Gating Control Through Speculative Instruction Window Weighting
  • Dynamic Capacity-Speed Tradeoffs in SMT Processor Caches
  • Branch History Matching: Branch Predictor Warmup for Sampled Simulation
  • Sunflower : Full-System, Embedded Microarchitecture Evaluation
  • Efficient Program Power Behavior Characterization
  • Generation of Efficient Embedded Applications
  • Performance/Energy Optimization of DSP Transforms on the XScale Processor
  • Arx: A Toolset for the Efficient Simulation and Direct Synthesis of High-Performance Signal Processing Algorithms
  • A Throughput-Driven Task Creation and Mapping for Network Processors
  • Optimizations and Architectural Tradeoffs for Embedded Systems
  • MiDataSets: Creating the Conditions for a More Realistic Evaluation of Iterative Optimization
  • Evaluation of Offset Assignment Heuristics
  • Customizing the Datapath and ISA of Soft VLIW Processors
  • Instruction Set Extension Generation with Considering Physical Constraints.

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