High Performance Embedded Architectures and Compilers Second International Conference, HiPEAC 2007, Ghent, Belgium, January 28-30, 2007. Proceedings /
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| Autor corporatiu: | |
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| Altres autors: | , , , , |
| Format: | Electrònic eBook |
| Idioma: | English |
| Publicat: |
Berlin, Heidelberg :
Springer Berlin Heidelberg : Imprint: Springer,
2007.
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| Edició: | 1st ed. 2007. |
| Periòdiques: | Theoretical Computer Science and General Issues ;
4367 |
| Matèries: | |
| Accés en línia: | https://doi.org/10.1007/978-3-540-69338-3 |
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Taula de continguts:
- Invited Program
- Keynote: Insight, Not (Random) Numbers: An Embedded Perspective
- I Secure and Low-Power Embedded Memory Systems
- Compiler-Assisted Memory Encryption for Embedded Processors
- Leveraging High Performance Data Cache Techniques to Save Power in Embedded Systems
- Applying Decay to Reduce Dynamic Power in Set-Associative Caches
- II Architecture/Compiler Optimizations for Efficient Embedded Processing
- Virtual Registers: Reducing Register Pressure Without Enlarging the Register File
- Bounds Checking with Taint-Based Analysis
- Reducing Exit Stub Memory Consumption in Code Caches
- III Adaptive Microarchitectures
- Reducing Branch Misprediction Penalties Via Adaptive Pipeline Scaling
- Fetch Gating Control Through Speculative Instruction Window Weighting
- Dynamic Capacity-Speed Tradeoffs in SMT Processor Caches
- Branch History Matching: Branch Predictor Warmup for Sampled Simulation
- Sunflower : Full-System, Embedded Microarchitecture Evaluation
- Efficient Program Power Behavior Characterization
- Generation of Efficient Embedded Applications
- Performance/Energy Optimization of DSP Transforms on the XScale Processor
- Arx: A Toolset for the Efficient Simulation and Direct Synthesis of High-Performance Signal Processing Algorithms
- A Throughput-Driven Task Creation and Mapping for Network Processors
- Optimizations and Architectural Tradeoffs for Embedded Systems
- MiDataSets: Creating the Conditions for a More Realistic Evaluation of Iterative Optimization
- Evaluation of Offset Assignment Heuristics
- Customizing the Datapath and ISA of Soft VLIW Processors
- Instruction Set Extension Generation with Considering Physical Constraints.