70-Gb/s amplitude-shift-keyed system with 10-GHz clock recovery circuit using duty cycle division multiplexing
The performance of ASK over DCDM for up to seven channels is reported. The aggregate bit rate of 70 Gb/s is achieved with only 160-GHz modulation bandwidth. The clock and data recovery are realized at 10-GHz clock rate, which is very economic and efficient. At 7 × 10 Gb/s, the worst receiver sensiti...
Saved in:
| Main Authors: | , , , , , , |
|---|---|
| Format: | Article |
| Language: | English |
| Published: |
Springer
2010
|
| Online Access: | http://psasir.upm.edu.my/id/eprint/11439/1/70.pdf |
| Tags: |
Add Tag
No Tags, Be the first to tag this record!
|