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Optimality of bus-invert coding

Dynamic power dissipation on I/O buses is an important issue for high-speed communication between chips. One can use coding techniques to reduce the number of transitions, which will reduce the dynamic power. Bus-invert coding is one popular technique for interchip buses, where the dominant contribu...

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Main Authors: Rokhani, Fakhrul Zaman, Kan, Wen Chih, Kieffer, John, Sobelman, Gerald E.
Format: Article
Language:English
English
Published: Institute of Electrical and Electronics Engineers Inc. 2009
Online Access:http://psasir.upm.edu.my/id/eprint/15953/1/Optimality%20of%20bus.pdf
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spelling oai:psasir.upm.edu.my:15953 http://psasir.upm.edu.my/id/eprint/15953/ Optimality of bus-invert coding Rokhani, Fakhrul Zaman Kan, Wen Chih Kieffer, John Sobelman, Gerald E. Dynamic power dissipation on I/O buses is an important issue for high-speed communication between chips. One can use coding techniques to reduce the number of transitions, which will reduce the dynamic power. Bus-invert coding is one popular technique for interchip buses, where the dominant contribution is from the self-capacitance of the wires. This algorithm uses an invert line to signal whether the bus data are in its original or an inverted form. While the method appears to be a greedy algorithm, we show that it is, in fact, an optimal strategy. To do so, we first represent the bus and invert line using a trellis diagram. Then, we show that applying bus-invert coding to a sequence of words gives the same result as would be obtained by using the Viterbi algorithm, which is known to be optimal. We also show that partitioning an M-bit bus into P subbuses and using bus-invert coding on each subbus can be described as applying the Viterbi algorithm on a 2P-state trellis. Institute of Electrical and Electronics Engineers Inc. 2009 Article PeerReviewed application/pdf en http://psasir.upm.edu.my/id/eprint/15953/1/Optimality%20of%20bus.pdf Rokhani, Fakhrul Zaman and Kan, Wen Chih and Kieffer, John and Sobelman, Gerald E. (2009) Optimality of bus-invert coding. IEEE Transactions on Circuits and Systems II: Express Briefs, 55 (11). pp. 1134-1138. ISSN 1549-7747; ESSN: 1558-3791 10.1109/TCSII.2008.2002564 English
institution UPM IR
collection UPM IR
language English
English
description Dynamic power dissipation on I/O buses is an important issue for high-speed communication between chips. One can use coding techniques to reduce the number of transitions, which will reduce the dynamic power. Bus-invert coding is one popular technique for interchip buses, where the dominant contribution is from the self-capacitance of the wires. This algorithm uses an invert line to signal whether the bus data are in its original or an inverted form. While the method appears to be a greedy algorithm, we show that it is, in fact, an optimal strategy. To do so, we first represent the bus and invert line using a trellis diagram. Then, we show that applying bus-invert coding to a sequence of words gives the same result as would be obtained by using the Viterbi algorithm, which is known to be optimal. We also show that partitioning an M-bit bus into P subbuses and using bus-invert coding on each subbus can be described as applying the Viterbi algorithm on a 2P-state trellis.
format Article
author Rokhani, Fakhrul Zaman
Kan, Wen Chih
Kieffer, John
Sobelman, Gerald E.
spellingShingle Rokhani, Fakhrul Zaman
Kan, Wen Chih
Kieffer, John
Sobelman, Gerald E.
Optimality of bus-invert coding
author_facet Rokhani, Fakhrul Zaman
Kan, Wen Chih
Kieffer, John
Sobelman, Gerald E.
author_sort Rokhani, Fakhrul Zaman
title Optimality of bus-invert coding
title_short Optimality of bus-invert coding
title_full Optimality of bus-invert coding
title_fullStr Optimality of bus-invert coding
title_full_unstemmed Optimality of bus-invert coding
title_sort optimality of bus-invert coding
publisher Institute of Electrical and Electronics Engineers Inc.
publishDate 2009
url http://psasir.upm.edu.my/id/eprint/15953/1/Optimality%20of%20bus.pdf
_version_ 1819293976266539008
score 13.4562235

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