CMOS technology for increasing efficiency of clock gating techniques using tri-state buffer

Clock gating is an effective technique of decreasing dynamic power dissipation in synchronous design. One of the methods used to realize this goal is to mask the clock which goes to the unnecessary to use in specific time. This paper will present a comparative analysis of this clock gating technique...

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Bibliographic Details
Main Authors: Mohammed, Maan Hameed, Mohamed Khmag, Asem Ib., Rokhani, Fakhrul Zaman, Ramli, Abd Rahman
Format: Article
Published: Institute of Research and Development, Walailak University 2017
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