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A Pipelined Multi-core MIPS Machine Hardware Implementation and Correctness Proof /

by Kovalev, Mikhail., Kovalev, Mikhail., Müller, Silvia M., Paul, Wolfgang J.
Published 2014

Table of Contents: “... Memory Bytes -- Loads and Stores -- ISA Summary -- A Sequential Processor Design -- Software Conditions...”
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Concurrent Programming: Algorithms, Principles, and Foundations

by Raynal, Michel., Raynal, Michel.
Published 2013

Table of Contents: “... Memory Approach -- Chap. 10 - Transactional Memory -- Part V - On the Foundations Side: From Safe Bits...”
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Advanced Techniques in Computing Sciences and Software Engineering

Published 2010

Table of Contents: “... Evaluation of Image Watermarking Algorithms -- Implementation of Efficient seamless non-broadcast Routing...”
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Advances in Computer Systems Architecture 11th Asia-Pacific Conference, ACSAC 2006, Shanghai, China, September 6-8, 2006, Proceedings /

Published 2006

Table of Contents: “... for Coordinating Data-Parallel Programs (Position Statement) -- Implementations of Square-Root and Exponential...”
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High-Performance Computing 6th International Symposium, ISHPC 2005, Nara, Japan, September 7-9, 2005, First International Workshop on Advance Low Power Systems, ALPS 2006, Revised...

Published 2008

Table of Contents: “... -- Exploiting Execution Locality with a Decoupled Kilo-Instruction Processor -- Decoupled State-Execute...”
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Algorithms and Architectures for Parallel Processing 10th International Conference, ICA3PP 2010, Busan, Korea, May 21-23, 2010. Proceedings, Part I /

Published 2010

Table of Contents: “... CMPs -- Network-on-Chip Routing Algorithms by Breaking Cycles -- A Fair Thread-Aware Memory Scheduling...”
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Hybrid Systems: Computation and Control 11th International Workshop, HSCC 2008, St. Louis, MO, USA, April 22-24, 2008, Proceedings /

Published 2008

Table of Contents: “... Closed-Loop Hybrid System -- Controller Synthesis with Budget Constraints -- Trading Infinite Memory...”
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Languages and Compilers for High Performance Computing 17th International Workshop, LCPC 2004, West Lafayette, IN, USA, September 22-24, 2004, Revised Selected Papers /

Published 2005

Table of Contents: “... SPEC2000FP Benchmarks -- An Offline Approach for Whole-Program Paths Analysis Using Suffix Arrays...”
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Compiler Construction 14th International Conference, CC 2005, Held as Part of the Joint European Conferences on Theory and Practice of Software, ETAPS 2005, Edinburgh, UK, April 4-...

Published 2005

Table of Contents: “... Languages with Modest Programming Effort -- Compilation of Generic Regular Path Expressions Using C++ Class...”
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Power-Aware Computer Systems Third International Workshop, PACS 2003, San Diego, CA, USA, December 1, 2003, Revised Papers /

Published 2005

Table of Contents: “... -- The Synergy Between Power-Aware Memory Systems and Processor Voltage Scaling -- Hot-and-Cold: Using...”
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Algorithms and Architectures for Parallel Processing 8th International Conference, ICA3PP 2008, Agia Napa, Cyprus, June 9-11, 2008, Proceedings /

Published 2008

Table of Contents: “... -- An Operational Approach to Validate the Path of BGP -- 1-Persistent Collision-Free CSMA Protocols...”
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Algorithms and Architectures for Parallel Processing 10th International Conference, ICA3PP 2010, Busan, Korea, May 21-23, 2010. Workshops, Part II /

Published 2010

Table of Contents: “...) -- Efficient Grid on the OTIS-Arrangment Network -- Single Thread Program Parallelism with Dataflow Abstracting...”
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Distributed Computing and Networking 8th International Conference, ICDCN 2006, Guwahati, India, December 27-30, 2006, Proceedings /

Published 2006

Table of Contents: “... Framework to Measure Robustness of Peer-to-Peer Networks -- Design and Implementation of a Network Processor...”
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High Performance Computing - HiPC 2004 11th International Conference, Bangalore, India, December 19-22, 2004, Proceedings /

Published 2005

Table of Contents: “... Point Using Intel’s IXP1200 Network Processor -- MuSeQoR: Multi-path Failure-Tolerant Security-Aware QoS...”
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High Performance Computing and Communications Second International Conference, HPCC 2006, Munich, Germany, September 13-15, 2006, Proceedings /

Published 2006

Table of Contents: “... and Implementation of Zero-Copy Data Path for Efficient File Transmission -- Virtual Hierarchy Synthesis for Hybrid...”
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Information Processing and Management International Conference on Recent Trends in Business Administration and Information Processing, BAIP 2010, Trivandrum, Kerala, India, March 2...

Published 2010

Table of Contents: “... and Implementation of an Efficient Method for Certificate Path Verification in Hierarchical Public Key...”
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Computer Science -- Theory and Applications First International Symposium on Computer Science in Russia, CSR 2006, St. Petersburg, Russia, June 8-12, 2006, Proceedings /

Published 2006

Table of Contents: “... Parallel ML: Semantics and Implementation of the Parallel Juxtaposition -- A Shortest Path Algorithm Based...”
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Network and Parallel Computing IFIP International Conference, NPC 2007, Dalian, China, September 18-21, 2007, Proceedings /

Published 2007

Table of Contents: “... of a Time-Dependent System on a Distributed Memory Processor -- Dynamic Multi-resource Advance...”
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Network and Parallel Computing 10th IFIP International Conference, NPC 2013, Guiyang, China, September 19-21, 2013, Proceedings /

Published 2013

Table of Contents: “... Environments -- A Fine-Grained Pipelined Implementation of LU Decomposition on SIMD Processors -- FRESA: A...”
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Network and Parallel Computing IFIP International Conference, NPC 2005, Beijing, China, November 30 - December 3, 2005, Proceedings /

Published 2005

Table of Contents: “... Optical Networks -- A Parallel O(n27n/8) Time-Memory-Processor Tradeoff for Knapsack-Like Problems...”
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