Low Power Networks-on-Chip
Low Power Networks-on-Chip Edited by: (editors) Cristina Silvano Marcello Lajolo Gianluca Palermo In recent years, both Networks-on-Chip, as an architectural solution for high-speed interconnect, and power consumption, as a key design constraint, have continued to gain interest in the design and res...
Gorde:
| Erakunde egilea: | |
|---|---|
| Beste egile batzuk: | , , |
| Formatua: | Baliabide elektronikoa eBook |
| Hizkuntza: | English |
| Argitaratua: |
New York, NY :
Springer US : Imprint: Springer,
2011.
|
| Edizioa: | 1st ed. 2011. |
| Gaiak: | |
| Sarrera elektronikoa: | https://doi.org/10.1007/978-1-4419-6911-8 |
| Etiketak: |
Etiketa erantsi
Etiketarik gabe, Izan zaitez lehena erregistro honi etiketa jartzen!
|
Aurkibidea:
- Network-on-Chip Power Estimation
- Timing
- synchronous/asynchronous communication
- Network-on-Chip link design
- Topology exploration
- Network-on-Chip support for CMP/MPSoCs
- Network design for 3D stacked logic and memory
- Beyond the wired Network-on-Chip.