Low Power Networks-on-Chip
Low Power Networks-on-Chip Edited by: (editors) Cristina Silvano Marcello Lajolo Gianluca Palermo In recent years, both Networks-on-Chip, as an architectural solution for high-speed interconnect, and power consumption, as a key design constraint, have continued to gain interest in the design and res...
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| 団体著者: | |
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| その他の著者: | , , |
| フォーマット: | 電子媒体 eBook |
| 言語: | English |
| 出版事項: |
New York, NY :
Springer US : Imprint: Springer,
2011.
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| 版: | 1st ed. 2011. |
| 主題: | |
| オンライン･アクセス: | https://doi.org/10.1007/978-1-4419-6911-8 |
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目次:
- Network-on-Chip Power Estimation
- Timing
- synchronous/asynchronous communication
- Network-on-Chip link design
- Topology exploration
- Network-on-Chip support for CMP/MPSoCs
- Network design for 3D stacked logic and memory
- Beyond the wired Network-on-Chip.