Routing Congestion in VLSI Circuits Estimation and Optimization /
With the dramatic increases in on-chip packing densities, routing congestion has become a major problem in chip design. The problem is especially acute as interconnects are also the performance bottleneck in integrated circuits. The solution lies in judicious resource management. This involves intel...
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| Main Authors: | , , |
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| 企業作者: | |
| 格式: | 電子 電子書 |
| 語言: | English |
| 出版: |
New York, NY :
Springer US : Imprint: Springer,
2007.
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| 版: | 1st ed. 2007. |
| 叢編: | Integrated Circuits and Systems,
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| 主題: | |
| 在線閱讀: | https://doi.org/10.1007/0-387-48550-3 |
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書本目錄:
- The Origins of Congestion
- An Introduction to Routing Congestion
- The Estimation of Congestion
- Placement-level Metrics for Routing Congestion
- Synthesis-level Metrics for Routing Congestion
- The Optimization of Congestion
- Congestion Optimization During Interconnect Synthesis and Routing
- Congestion Optimization During Placement
- Congestion Optimization During Technology Mapping and Logic Synthesis
- Congestion Implications of High Level Design.