Routing Congestion in VLSI Circuits Estimation and Optimization /
With the dramatic increases in on-chip packing densities, routing congestion has become a major problem in chip design. The problem is especially acute as interconnects are also the performance bottleneck in integrated circuits. The solution lies in judicious resource management. This involves intel...
Wedi'i Gadw mewn:
| Prif Awduron: | , , |
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| Awdur Corfforaethol: | |
| Fformat: | Electronig eLyfr |
| Iaith: | English |
| Cyhoeddwyd: |
New York, NY :
Springer US : Imprint: Springer,
2007.
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| Rhifyn: | 1st ed. 2007. |
| Cyfres: | Integrated Circuits and Systems,
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| Pynciau: | |
| Mynediad Ar-lein: | https://doi.org/10.1007/0-387-48550-3 |
| Tagiau: |
Ychwanegu Tag
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Tabl Cynhwysion:
- The Origins of Congestion
- An Introduction to Routing Congestion
- The Estimation of Congestion
- Placement-level Metrics for Routing Congestion
- Synthesis-level Metrics for Routing Congestion
- The Optimization of Congestion
- Congestion Optimization During Interconnect Synthesis and Routing
- Congestion Optimization During Placement
- Congestion Optimization During Technology Mapping and Logic Synthesis
- Congestion Implications of High Level Design.