Routing Congestion in VLSI Circuits Estimation and Optimization /
With the dramatic increases in on-chip packing densities, routing congestion has become a major problem in chip design. The problem is especially acute as interconnects are also the performance bottleneck in integrated circuits. The solution lies in judicious resource management. This involves intel...
Na minha lista:
| Main Authors: | , , |
|---|---|
| Autor Corporativo: | |
| Formato: | Recurso Electrónico livro electrónico |
| Idioma: | English |
| Publicado em: |
New York, NY :
Springer US : Imprint: Springer,
2007.
|
| Edição: | 1st ed. 2007. |
| Colecção: | Integrated Circuits and Systems,
|
| Assuntos: | |
| Acesso em linha: | https://doi.org/10.1007/0-387-48550-3 |
| Tags: |
Adicionar Tag
Sem tags, seja o primeiro a adicionar uma tag!
|
Seja o primeiro a partilhar um comentário!