Routing Congestion in VLSI Circuits Estimation and Optimization /
With the dramatic increases in on-chip packing densities, routing congestion has become a major problem in chip design. The problem is especially acute as interconnects are also the performance bottleneck in integrated circuits. The solution lies in judicious resource management. This involves intel...
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| Autors principals: | , , |
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| Autor corporatiu: | |
| Format: | Electrònic eBook |
| Idioma: | English |
| Publicat: |
New York, NY :
Springer US : Imprint: Springer,
2007.
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| Edició: | 1st ed. 2007. |
| Periòdiques: | Integrated Circuits and Systems,
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| Matèries: | |
| Accés en línia: | https://doi.org/10.1007/0-387-48550-3 |
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