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Routing Congestion in VLSI Circuits Estimation and Optimization /

With the dramatic increases in on-chip packing densities, routing congestion has become a major problem in chip design. The problem is especially acute as interconnects are also the performance bottleneck in integrated circuits. The solution lies in judicious resource management. This involves intel...

Täydet tiedot

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Bibliografiset tiedot
Päätekijät: Saxena, Prashant. (Tekijä, http://id.loc.gov/vocabulary/relators/aut), Shelar, Rupesh S. (http://id.loc.gov/vocabulary/relators/aut), Sapatnekar, Sachin. (http://id.loc.gov/vocabulary/relators/aut)
Yhteisötekijä: SpringerLink (Online service)
Aineistotyyppi: Elektroninen E-kirja
Kieli:English
Julkaistu: New York, NY : Springer US : Imprint: Springer, 2007.
Painos:1st ed. 2007.
Sarja:Integrated Circuits and Systems,
Aiheet:
Electronic circuits.
Computer-aided engineering.
Electrical engineering.
Circuits and Systems.
Computer-Aided Engineering (CAD, CAE) and Design.
Communications Engineering, Networks.
Linkit:https://doi.org/10.1007/0-387-48550-3
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https://doi.org/10.1007/0-387-48550-3

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