Image de couverture de livre

Routing Congestion in VLSI Circuits Estimation and Optimization /

With the dramatic increases in on-chip packing densities, routing congestion has become a major problem in chip design. The problem is especially acute as interconnects are also the performance bottleneck in integrated circuits. The solution lies in judicious resource management. This involves intel...

Description complète

Enregistré dans:
Détails bibliographiques
Auteurs principaux: Saxena, Prashant. (Auteur, http://id.loc.gov/vocabulary/relators/aut), Shelar, Rupesh S. (http://id.loc.gov/vocabulary/relators/aut), Sapatnekar, Sachin. (http://id.loc.gov/vocabulary/relators/aut)
Collectivité auteur: SpringerLink (Online service)
Format: Électronique eBook
Langue:English
Publié: New York, NY : Springer US : Imprint: Springer, 2007.
Édition:1st ed. 2007.
Collection:Integrated Circuits and Systems,
Sujets:
Electronic circuits.
Computer-aided engineering.
Electrical engineering.
Circuits and Systems.
Computer-Aided Engineering (CAD, CAE) and Design.
Communications Engineering, Networks.
Accès en ligne:https://doi.org/10.1007/0-387-48550-3
Tags: Ajouter un tag
Pas de tags, Soyez le premier à ajouter un tag!

Internet

https://doi.org/10.1007/0-387-48550-3

Documents similaires