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Routing Congestion in VLSI Circuits Estimation and Optimization /

With the dramatic increases in on-chip packing densities, routing congestion has become a major problem in chip design. The problem is especially acute as interconnects are also the performance bottleneck in integrated circuits. The solution lies in judicious resource management. This involves intel...

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Główni autorzy: Saxena, Prashant. (Autor, http://id.loc.gov/vocabulary/relators/aut), Shelar, Rupesh S. (http://id.loc.gov/vocabulary/relators/aut), Sapatnekar, Sachin. (http://id.loc.gov/vocabulary/relators/aut)
Korporacja: SpringerLink (Online service)
Format: Elektroniczne E-book
Język:English
Wydane: New York, NY : Springer US : Imprint: Springer, 2007.
Wydanie:1st ed. 2007.
Seria:Integrated Circuits and Systems,
Hasła przedmiotowe:
Electronic circuits.
Computer-aided engineering.
Electrical engineering.
Circuits and Systems.
Computer-Aided Engineering (CAD, CAE) and Design.
Communications Engineering, Networks.
Dostęp online:https://doi.org/10.1007/0-387-48550-3
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https://doi.org/10.1007/0-387-48550-3

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